From: Elaine Zhang Date: Fri, 17 Mar 2017 02:57:51 +0000 (+0800) Subject: clk: rockchip: rk3368: add CLK_SET_RATE_PARENT flag for dclk_vop X-Git-Tag: firefly_0821_release~295 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d072a98be59b8d35538c95947b65404eadc42eaf;p=firefly-linux-kernel-4.4.55.git clk: rockchip: rk3368: add CLK_SET_RATE_PARENT flag for dclk_vop dclk_vop only allowed on NPLL. Change-Id: I5325a530d3052de1e8685c39b90357291f0f4fb3 Signed-off-by: Elaine Zhang --- diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 279c72b59b67..86dd3646fd7c 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -105,6 +105,7 @@ PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" }; PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; +PNAME(mux_pll_src_dmycpll_dmygpll_npll_p) = { "dummy_cpll", "dummy_gpll", "npll" }; PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" }; PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m", @@ -458,7 +459,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3368_CLKGATE_CON(4), 4, GFLAGS), - COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3368_CLKGATE_CON(4), 1, GFLAGS),