From: Colin LeMahieu Date: Fri, 16 Jan 2015 21:41:57 +0000 (+0000) Subject: [Hexagon] Converting halfword to doubleword multiply intrinsics. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d08a6cd0836866b6ad78ef9c0b89317c2e7a0915;p=oota-llvm.git [Hexagon] Converting halfword to doubleword multiply intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226326 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td index df40a832088..e559b4d58c3 100644 --- a/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/lib/Target/Hexagon/HexagonIntrinsics.td @@ -132,6 +132,39 @@ def : T_RRR_pat ; def : T_RRR_pat ; def : T_RRR_pat ; + +//===----------------------------------------------------------------------===// +// Multiply signed/unsigned halfwords with and without saturation and rounding +// into a 64-bits destination register. +//===----------------------------------------------------------------------===// + +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; + +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; + +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; + // // ALU 32 types. // @@ -2685,43 +2718,6 @@ def HEXAGON_M2_dpmpyss_nac_s0: * MTYPE/MPYS * *********************************************************************/ -//Rdd=mpy(Rs.[H|L],Rt.[H|L])[[:<<0|:<<1]|[:<<0:rnd|:<<1:rnd]] -def HEXAGON_M2_mpyd_hh_s0: - di_MInst_sisi_hh <"mpy", int_hexagon_M2_mpyd_hh_s0>; -def HEXAGON_M2_mpyd_hh_s1: - di_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpyd_hh_s1>; -def HEXAGON_M2_mpyd_rnd_hh_s1: - di_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hh_s1>; -def HEXAGON_M2_mpyd_rnd_hh_s0: - di_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpyd_rnd_hh_s0>; - -def HEXAGON_M2_mpyd_hl_s0: - di_MInst_sisi_hl <"mpy", int_hexagon_M2_mpyd_hl_s0>; -def HEXAGON_M2_mpyd_hl_s1: - di_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpyd_hl_s1>; -def HEXAGON_M2_mpyd_rnd_hl_s1: - di_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hl_s1>; -def HEXAGON_M2_mpyd_rnd_hl_s0: - di_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpyd_rnd_hl_s0>; - -def HEXAGON_M2_mpyd_lh_s0: - di_MInst_sisi_lh <"mpy", int_hexagon_M2_mpyd_lh_s0>; -def HEXAGON_M2_mpyd_lh_s1: - di_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpyd_lh_s1>; -def HEXAGON_M2_mpyd_rnd_lh_s1: - di_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_lh_s1>; -def HEXAGON_M2_mpyd_rnd_lh_s0: - di_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpyd_rnd_lh_s0>; - -def HEXAGON_M2_mpyd_ll_s0: - di_MInst_sisi_ll <"mpy", int_hexagon_M2_mpyd_ll_s0>; -def HEXAGON_M2_mpyd_ll_s1: - di_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpyd_ll_s1>; -def HEXAGON_M2_mpyd_rnd_ll_s1: - di_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpyd_rnd_ll_s1>; -def HEXAGON_M2_mpyd_rnd_ll_s0: - di_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpyd_rnd_ll_s0>; - //Rx+=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1] def HEXAGON_M2_mpyd_acc_hh_s0: di_MInst_disisi_acc_hh <"mpy", int_hexagon_M2_mpyd_acc_hh_s0>; diff --git a/test/CodeGen/Hexagon/intrinsics-mpyd.ll b/test/CodeGen/Hexagon/intrinsics-mpyd.ll new file mode 100644 index 00000000000..d85fc7adb42 --- /dev/null +++ b/test/CodeGen/Hexagon/intrinsics-mpyd.ll @@ -0,0 +1,270 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s + +; Verify that the mpy intrinsics are lowered into the right instructions. +; These instructions have a 64-bit destination register. + +@c = external global i64 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h) + +define void @test1(i32 %a1, i32 %b1) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.hh.s0(i32 %a1, i32 %b1) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.hh.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l) + +define void @test2(i32 %a2, i32 %b2) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.hl.s0(i32 %a2, i32 %b2) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.hl.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h) + +define void @test3(i32 %a3, i32 %b3) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.lh.s0(i32 %a3, i32 %b3) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.lh.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l) + +define void @test4(i32 %a4, i32 %b4) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.ll.s0(i32 %a4, i32 %b4) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.ll.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1 + +define void @test5(i32 %a5, i32 %b5) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.hh.s1(i32 %a5, i32 %b5) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.hh.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1 + +define void @test6(i32 %a6, i32 %b6) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.hl.s1(i32 %a6, i32 %b6) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.hl.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1 + +define void @test7(i32 %a7, i32 %b7) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.lh.s1(i32 %a7, i32 %b7) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.lh.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1 + +define void @test8(i32 %a8, i32 %b8) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.ll.s1(i32 %a8, i32 %b8) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):rnd + +define void @test9(i32 %a9, i32 %b9) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32 %a9, i32 %b9) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):rnd + +define void @test10(i32 %a10, i32 %b10) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32 %a10, i32 %b10) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):rnd + +define void @test11(i32 %a11, i32 %b11) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32 %a11, i32 %b11) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):rnd + +define void @test12(i32 %a12, i32 %b12) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32 %a12, i32 %b12) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd + +define void @test13(i32 %a13, i32 %b13) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32 %a13, i32 %b13) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd + +define void @test14(i32 %a14, i32 %b14) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32 %a14, i32 %b14) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd + +define void @test15(i32 %a15, i32 %b15) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32 %a15, i32 %b15) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd + +define void @test16(i32 %a16, i32 %b16) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32 %a16, i32 %b16) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h) + +define void @test17(i32 %a17, i32 %b17) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyud.hh.s0(i32 %a17, i32 %b17) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyud.hh.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l) + +define void @test18(i32 %a18, i32 %b18) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyud.hl.s0(i32 %a18, i32 %b18) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyud.hl.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h) + +define void @test19(i32 %a19, i32 %b19) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyud.lh.s0(i32 %a19, i32 %b19) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyud.lh.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l) + +define void @test20(i32 %a20, i32 %b20) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyud.ll.s0(i32 %a20, i32 %b20) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyud.ll.s0(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1 + +define void @test21(i32 %a21, i32 %b21) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyud.hh.s1(i32 %a21, i32 %b21) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyud.hh.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1 + +define void @test22(i32 %a22, i32 %b22) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyud.hl.s1(i32 %a22, i32 %b22) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyud.hl.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1 + +define void @test23(i32 %a23, i32 %b23) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyud.lh.s1(i32 %a23, i32 %b23) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyud.lh.s1(i32, i32) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1 + +define void @test24(i32 %a24, i32 %b24) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.M2.mpyud.ll.s1(i32 %a24, i32 %b24) + store i64 %0, i64* @c, align 8 + ret void +} + +declare i64 @llvm.hexagon.M2.mpyud.ll.s1(i32, i32) #1