From: Soren Brinkmann Date: Wed, 19 Dec 2012 18:18:39 +0000 (-0800) Subject: arm: zynq: timer: Align columns X-Git-Tag: firefly_0821_release~3680^2~1075^2~16^2~3 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d16aaf47ee2e668cc68a881bb957f0a7273d30ab;p=firefly-linux-kernel-4.4.55.git arm: zynq: timer: Align columns Aligning the columns in a block of #defines, so that the values are starting in the same colum on every line. Signed-off-by: Soren Brinkmann Tested-by: Josh Cartwright --- diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index 80bf4742fe37..4b81ae1153d3 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -35,9 +35,9 @@ * Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 */ -#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ -#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ -#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ +#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ +#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ #define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ #define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ #define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */