From: Vikram S. Adve <vadve@cs.uiuc.edu>
Date: Tue, 21 Oct 2003 12:29:45 +0000 (+0000)
Subject: When opcodes like ADD were split into reg. and immed. versions (ADDi and ADDr),
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d248652b8beaef52b1b256fa52092967f1b0f6ef;p=oota-llvm.git

When opcodes like ADD were split into reg. and immed. versions (ADDi and ADDr),
this code wasn't fixed correctly so it missed copy operations that used ADDi.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9318 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
index 2b22558e6dc..9d50f35f541 100644
--- a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
+++ b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
@@ -63,7 +63,8 @@ static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
     return (/* both operands are allocated to the same register */
             MI->getOperand(0).getAllocatedRegNum() == 
             MI->getOperand(1).getAllocatedRegNum());
-  } else if (MI->getOpCode() == V9::ADDr || MI->getOpCode() == V9::ORr) {
+  } else if (MI->getOpCode() == V9::ADDr || MI->getOpCode() == V9::ORr ||
+             MI->getOpCode() == V9::ADDi || MI->getOpCode() == V9::ORi) {
     unsigned srcWithDestReg;
     
     for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)