From: Misha Brukman <brukman+llvm@gmail.com>
Date: Fri, 25 Jun 2004 19:04:27 +0000 (+0000)
Subject: Do not move any values into registers for a void return (there isn't anything).
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d47bbf7ce53ada1c6a810de82987a05db725f13d;p=oota-llvm.git

Do not move any values into registers for a void return (there isn't anything).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14413 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index a75a4b0aaae..4302beb79b3 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -1062,26 +1062,29 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
 /// visitReturnInst - implemented with BLR
 ///
 void ISel::visitReturnInst(ReturnInst &I) {
-  Value *RetVal = I.getOperand(0);
-  switch (getClassB(RetVal->getType())) {
-  case cByte:   // integral return values: extend or move into r3 and return
-  case cShort:
-  case cInt:
-    promote32(PPC32::R3, ValueRecord(RetVal));
-    break;
-  case cFP: {   // Floats & Doubles: Return in f1
-    unsigned RetReg = getReg(RetVal);
-    BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
-    break;
-  }
-  case cLong: {
-    unsigned RetReg = getReg(RetVal);
-    BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
-    BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
-    break;
-  }
-  default:
-    visitInstruction(I);
+  // Only do the processing if this is a non-void return
+  if (I.getNumOperands() > 0) {
+    Value *RetVal = I.getOperand(0);
+    switch (getClassB(RetVal->getType())) {
+    case cByte:   // integral return values: extend or move into r3 and return
+    case cShort:
+    case cInt:
+      promote32(PPC32::R3, ValueRecord(RetVal));
+      break;
+    case cFP: {   // Floats & Doubles: Return in f1
+      unsigned RetReg = getReg(RetVal);
+      BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
+      break;
+    }
+    case cLong: {
+      unsigned RetReg = getReg(RetVal);
+      BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
+      BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
+      break;
+    }
+    default:
+      visitInstruction(I);
+    }
   }
   BuildMI(BB, PPC32::BLR, 1).addImm(0);
 }
diff --git a/lib/Target/PowerPC/PowerPCISelSimple.cpp b/lib/Target/PowerPC/PowerPCISelSimple.cpp
index a75a4b0aaae..4302beb79b3 100644
--- a/lib/Target/PowerPC/PowerPCISelSimple.cpp
+++ b/lib/Target/PowerPC/PowerPCISelSimple.cpp
@@ -1062,26 +1062,29 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
 /// visitReturnInst - implemented with BLR
 ///
 void ISel::visitReturnInst(ReturnInst &I) {
-  Value *RetVal = I.getOperand(0);
-  switch (getClassB(RetVal->getType())) {
-  case cByte:   // integral return values: extend or move into r3 and return
-  case cShort:
-  case cInt:
-    promote32(PPC32::R3, ValueRecord(RetVal));
-    break;
-  case cFP: {   // Floats & Doubles: Return in f1
-    unsigned RetReg = getReg(RetVal);
-    BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
-    break;
-  }
-  case cLong: {
-    unsigned RetReg = getReg(RetVal);
-    BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
-    BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
-    break;
-  }
-  default:
-    visitInstruction(I);
+  // Only do the processing if this is a non-void return
+  if (I.getNumOperands() > 0) {
+    Value *RetVal = I.getOperand(0);
+    switch (getClassB(RetVal->getType())) {
+    case cByte:   // integral return values: extend or move into r3 and return
+    case cShort:
+    case cInt:
+      promote32(PPC32::R3, ValueRecord(RetVal));
+      break;
+    case cFP: {   // Floats & Doubles: Return in f1
+      unsigned RetReg = getReg(RetVal);
+      BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
+      break;
+    }
+    case cLong: {
+      unsigned RetReg = getReg(RetVal);
+      BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
+      BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
+      break;
+    }
+    default:
+      visitInstruction(I);
+    }
   }
   BuildMI(BB, PPC32::BLR, 1).addImm(0);
 }