From: dkl <dkl@rock-chips.com>
Date: Fri, 12 Dec 2014 02:25:26 +0000 (+0800)
Subject: clk: rockchip: fix pll_clk_get_best_set() for rk3188plus type pll
X-Git-Tag: firefly_0821_release~4386
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d52ba29d14cc617c25f72bfbdf802147caa8eb06;p=firefly-linux-kernel-4.4.55.git

clk: rockchip: fix pll_clk_get_best_set() for rk3188plus type pll

When selecting a best setting for rk3188plus type pll, consider a
larger NO first(means larger VCO freq), and a smaller NR later.

Signed-off-by: dkl <dkl@rock-chips.com>
---

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 40a2f9873e95..09b627e7a170 100755
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1025,7 +1025,7 @@ static int pll_clk_get_best_set(unsigned long fin_hz, unsigned long fout_hz,
 		       //printk("_PLL_SET_CLKS(%lu,\t%d,\t%d,\t%d),\n",fout_hz/KHZ,nr,nf,no);
 
 		       /* select the best from all available PLL settings */
-		       if((nr < nr_out) || ((nr == nr_out)&&(no > no_out)))
+		       if ((no > no_out) || ((no == no_out) && (nr < nr_out)))
 		       {
 			       nr_out = nr;
 			       nf_out = nf;