From: dkl <dkl@rock-chips.com>
Date: Wed, 30 Apr 2014 01:23:30 +0000 (+0800)
Subject: rk3288: set RK3288_LIMIT_PLL_VIO1 to 410MHZ
X-Git-Tag: firefly_0821_release~5404
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d64a67250b6b9be3f1dadda4356a369a5f9c40ae;p=firefly-linux-kernel-4.4.55.git

rk3288: set RK3288_LIMIT_PLL_VIO1 to 410MHZ
---

diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index 4e7aef47321c..604a94f8b916 100644
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -616,7 +616,7 @@ const struct clk_ops clkops_rate_3288_dclk_lcdc0 = {
 	.recalc_rate	= clk_divider_recalc_rate,
 };
 
-#define RK3288_LIMIT_PLL_VIO1 (348*MHZ)
+#define RK3288_LIMIT_PLL_VIO1 (410*MHZ)
 
 static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long rate,
 		unsigned long *best_parent_rate,