From: Brian Gaeke Date: Thu, 30 Sep 2004 04:04:48 +0000 (+0000) Subject: Mark the instructions that have delay slots with the hasDelaySlot flag. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d7bf501cc732f8ddcc30a6bd68d2fdbfe0f2145f;p=oota-llvm.git Mark the instructions that have delay slots with the hasDelaySlot flag. Add some comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16611 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 979ba1638d0..5751f6f0260 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -47,9 +47,9 @@ def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move // Section A.3 - Synthetic Instructions, p. 85 // special cases of JMPL: -let isReturn = 1, isTerminator = 1, simm13 = 8 in +let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in def RET : F3_2<2, 0b111000, "ret">; -let isReturn = 1, isTerminator = 1, simm13 = 8 in +let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in def RETL: F3_2<2, 0b111000, "retl">; // CMP is a special case of SUBCC where destination is ignored, by setting it to // %g0 (hardwired zero). @@ -148,6 +148,7 @@ def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r class BranchV8 cc, string nm> : F2_2 { let isBranch = 1; let isTerminator = 1; + let hasDelaySlot = 1; } let isBarrier = 1 in @@ -170,6 +171,7 @@ def BCS : BranchV8<0b0101, "bcs">; class FPBranchV8 cc, string nm> : F2_2 { let isBranch = 1; let isTerminator = 1; + let hasDelaySlot = 1; } def FBA : FPBranchV8<0b1000, "fba">; @@ -191,14 +193,15 @@ def FBO : FPBranchV8<0b1111, "fbo">; // Section B.24 - Call and Link Instruction, p. 125 // This is the only Format 1 instruction -let Defs = [O0, O1, O2, O3, O4, O5] in -let isCall = 1 in { +let Defs = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { + // pc-relative call: def CALL : InstV8 { bits<30> disp; let op = 1; let Inst{29-0} = disp; let Name = "call"; } + // indirect call: def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd } @@ -233,9 +236,14 @@ def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; // Floating-point Compare Instructions, p. 148 -// Note: the 2nd template arg is different for these guys -def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; -def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; -def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; -def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; +// Note: the 2nd template arg is different for these guys. +// Note 2: the result of a FCMP is not available until the 2nd cycle +// after the instr is retired, but there is no interlock. This behavior +// is modelled as a delay slot. +let hasDelaySlot = 1 in { + def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; + def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; + def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; + def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; +} diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td index 979ba1638d0..5751f6f0260 100644 --- a/lib/Target/SparcV8/SparcV8InstrInfo.td +++ b/lib/Target/SparcV8/SparcV8InstrInfo.td @@ -47,9 +47,9 @@ def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move // Section A.3 - Synthetic Instructions, p. 85 // special cases of JMPL: -let isReturn = 1, isTerminator = 1, simm13 = 8 in +let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in def RET : F3_2<2, 0b111000, "ret">; -let isReturn = 1, isTerminator = 1, simm13 = 8 in +let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in def RETL: F3_2<2, 0b111000, "retl">; // CMP is a special case of SUBCC where destination is ignored, by setting it to // %g0 (hardwired zero). @@ -148,6 +148,7 @@ def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r class BranchV8 cc, string nm> : F2_2 { let isBranch = 1; let isTerminator = 1; + let hasDelaySlot = 1; } let isBarrier = 1 in @@ -170,6 +171,7 @@ def BCS : BranchV8<0b0101, "bcs">; class FPBranchV8 cc, string nm> : F2_2 { let isBranch = 1; let isTerminator = 1; + let hasDelaySlot = 1; } def FBA : FPBranchV8<0b1000, "fba">; @@ -191,14 +193,15 @@ def FBO : FPBranchV8<0b1111, "fbo">; // Section B.24 - Call and Link Instruction, p. 125 // This is the only Format 1 instruction -let Defs = [O0, O1, O2, O3, O4, O5] in -let isCall = 1 in { +let Defs = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { + // pc-relative call: def CALL : InstV8 { bits<30> disp; let op = 1; let Inst{29-0} = disp; let Name = "call"; } + // indirect call: def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd } @@ -233,9 +236,14 @@ def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; // Floating-point Compare Instructions, p. 148 -// Note: the 2nd template arg is different for these guys -def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; -def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; -def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; -def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; +// Note: the 2nd template arg is different for these guys. +// Note 2: the result of a FCMP is not available until the 2nd cycle +// after the instr is retired, but there is no interlock. This behavior +// is modelled as a delay slot. +let hasDelaySlot = 1 in { + def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; + def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; + def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; + def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; +}