From: Will Deacon Date: Mon, 13 May 2013 11:08:06 +0000 (+0100) Subject: ARM: kvm: use inner-shareable barriers after TLB flushing X-Git-Tag: firefly_0821_release~3680^2~36^2~16^2^2~234 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=d829a739332e33ffc9753c607325f461e9c994d8;p=firefly-linux-kernel-4.4.55.git ARM: kvm: use inner-shareable barriers after TLB flushing When flushing the TLB at PL2 in response to remapping at stage-2 or VMID rollover, we have a dsb instruction to ensure completion of the command before continuing. Since we only care about other processors for TLB invalidation, use the inner-shareable variant of the dsb instruction instead. Acked-by: Marc Zyngier Reviewed-by: Catalin Marinas Signed-off-by: Will Deacon (cherry picked from commit e3ab547f57bd626201d4b715b696c80ad1ef4ba2) Signed-off-by: Christoffer Dall --- diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S index f048338135f7..1b9844d369cc 100644 --- a/arch/arm/kvm/init.S +++ b/arch/arm/kvm/init.S @@ -142,7 +142,7 @@ target: @ We're now in the trampoline code, switch page tables @ Invalidate the old TLBs mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH - dsb + dsb ish eret diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S index 16cd4ba5d7fd..f85052facffc 100644 --- a/arch/arm/kvm/interrupts.S +++ b/arch/arm/kvm/interrupts.S @@ -55,7 +55,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa) mcrr p15, 6, r2, r3, c2 @ Write VTTBR isb mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS (rt ignored) - dsb + dsb ish isb mov r2, #0 mov r3, #0 @@ -79,7 +79,7 @@ ENTRY(__kvm_flush_vm_context) mcr p15, 4, r0, c8, c3, 4 /* Invalidate instruction caches Inner Shareable (ICIALLUIS) */ mcr p15, 0, r0, c7, c1, 0 - dsb + dsb ish isb @ Not necessary if followed by eret bx lr