From: John Kramer Date: Fri, 14 Jan 2011 14:04:58 +0000 (-0600) Subject: media: video: tegra: Correct mclk settings for ov5650 and soc2030 X-Git-Tag: firefly_0821_release~9834^2~160 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=dbfdd7ed28d1b2fbc101b15f9d8dbe1b5aa3f8a6;p=firefly-linux-kernel-4.4.55.git media: video: tegra: Correct mclk settings for ov5650 and soc2030 Change-Id: I8a7c1abf38313fb73256581d01f0245200f3b850 Signed-off-by: John Kramer --- diff --git a/drivers/media/video/tegra/ov5650.c b/drivers/media/video/tegra/ov5650.c index e19ca21e33c6..545e6db3952c 100644 --- a/drivers/media/video/tegra/ov5650.c +++ b/drivers/media/video/tegra/ov5650.c @@ -129,7 +129,7 @@ static struct ov5650_reg mode_start[] = { {0x300f, 0x8f}, /* PLL control00 R_SELD5 [7:6] div by 4 R_DIVL [2] two lane div 1 SELD2P5 [1:0] div 2.5 pg 99 */ {0x3010, 0x10}, /* PLL control01 DIVM [3:0] DIVS [7:4] div 1 pg 99 */ - {0x3011, 0x14}, /* PLL control02 R_DIVP [5:0] div 20 pg 99 */ + {0x3011, 0x18}, /* PLL control02 R_DIVP [5:0] div 24 pg 99 (20Mhz Mclk*/ {0x3012, 0x02}, /* PLL CTR 03, default */ {0x3815, 0x82}, /* PCLK to SCLK ratio bit[4:0] is set to 2 pg 81 */ {0x3503, 0x33}, /* AEC auto AGC auto gain has no latch delay. pg 38 */ diff --git a/drivers/media/video/tegra/soc2030.c b/drivers/media/video/tegra/soc2030.c index 05ec9e6112df..a4c98a586cf9 100644 --- a/drivers/media/video/tegra/soc2030.c +++ b/drivers/media/video/tegra/soc2030.c @@ -346,7 +346,7 @@ static struct soc2030_regs mode_1280x720[] = { static struct soc2030_regs pll_table[] = { {WRITE_REG_DATA, 0x001e, 0x0503}, /*Pad Slew rate*/ {WRITE_REG_DATA, 0x0014, 0x2545}, /*PLL_CONTROL*/ - {WRITE_REG_DATA, 0x0010, 0x011C}, /*PLL_DIVIDERS*/ + {WRITE_REG_DATA, 0x0010, 0x0a56}, /*PLL_DIVIDERS 43mhz*/ {WRITE_REG_DATA, 0x0012, 0x10F7}, /*PLL_P_DIVIDERS*/ {WRITE_REG_DATA, 0x0014, 0x2547}, /*PLL_CONTROL*/ {WRITE_REG_DATA, 0x0014, 0x2447}, /*PLL_CONTROL*/