From: Chris Lattner <sabre@nondot.org>
Date: Sat, 4 Feb 2006 02:26:14 +0000 (+0000)
Subject: Add initial support for immediates.  This allows us to compile this:
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=dc19b70d24e5fc0b80da36240550e31eb6ee4ee8;p=oota-llvm.git

Add initial support for immediates.  This allows us to compile this:

int %rlwnm(int %A, int %B) {
  %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
  ret int %C
}

into:

_rlwnm:
        or r2, r3, r3
        or r3, r4, r4
        rlwnm r2, r2, r3, 4, 17    ;; note the immediates :)
        or r3, r2, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25955 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index c0fd3975649..aff5d4265dd 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -300,16 +300,26 @@ void ScheduleDAG::EmitNode(NodeInfo *NI) {
       
       // Add all of the operand registers to the instruction.
       for (unsigned i = 2; i != NumOps; i += 2) {
-        unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
         unsigned Flags =cast<ConstantSDNode>(Node->getOperand(i+1))->getValue();
         MachineOperand::UseType UseTy;
         switch (Flags) {
         default: assert(0 && "Bad flags!");
-        case 1: UseTy = MachineOperand::Use; break;
-        case 2: UseTy = MachineOperand::Def; break;
-        case 3: UseTy = MachineOperand::UseAndDef; break;
+        case 1: { // Use of register.
+          unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+          MI->addMachineRegOperand(Reg, MachineOperand::Use);
+          break;
+        }
+        case 2: { // Def of register.
+          unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+          MI->addMachineRegOperand(Reg, MachineOperand::Def);
+          break;
+        }
+        case 3: { // Immediate.
+          uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
+          MI->addZeroExtImm64Operand(Val);
+          break;
+        }
         }
-        MI->addMachineRegOperand(Reg, UseTy);
       }
       break;
     }
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 47fb6c357d8..e4691b3d9c5 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1366,7 +1366,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
       
       // Add information to the INLINEASM node to know about this input.
       AsmNodeOperands.push_back(ResOp);
-      AsmNodeOperands.push_back(DAG.getConstant(1, MVT::i32)); // ISUSE
+      AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
       break;
     }
     case InlineAsm::isClobber: