From: Tom Stellard <thomas.stellard@amd.com>
Date: Thu, 9 Jul 2015 16:30:27 +0000 (+0000)
Subject: AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e05910e6770e95a1aee6d3ac4c5ced059a6e3c7f;p=oota-llvm.git

AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()

No test case for this.  I ran into it while working on some improvements
to SIShrinkInstructions.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241816 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp
index eb96bd0227b..288ab7523e3 100644
--- a/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1625,7 +1625,10 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
 
   if (MO->isReg()) {
     assert(DefinedRC);
-    const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
+    const TargetRegisterClass *RC =
+        TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
+            MRI.getRegClass(MO->getReg()) :
+            RI.getPhysRegClass(MO->getReg());
 
     // In order to be legal, the common sub-class must be equal to the
     // class of the current operand.  For example: