From: Akira Hatanaka Date: Thu, 26 Jul 2012 02:24:43 +0000 (+0000) Subject: Fix call setup for PIC. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e11246c64eb8ea3da0060be4ddb9596c8cc04439;p=oota-llvm.git Fix call setup for PIC. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160774 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index c85204278b8..70719e86493 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -46,6 +46,15 @@ class FEXT_RI16_ins _op, string asmstr, class FEXT_RI16_PC_ins _op, string asmstr, InstrItinClass itin>: FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; + +class FEXT_2RI16_ins _op, string asmstr, + InstrItinClass itin>: + FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), + !strconcat(asmstr, "\t$rx, $imm"), [], itin> { + let Constraints = "$rx_ = $rx"; +} + + // // RR-type instruction format // @@ -80,6 +89,20 @@ def mem16 : Operand { } // + +// Format: ADDIU rx, immediate MIPS16e +// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) +// To add a constant to a 32-bit integer. +// +class AddiuRxImmX16_base: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; +def AddiuRxImmX16: AddiuRxImmX16_base; + + +class AddiuRxRxImmX16_base: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>; +def AddiuRxRxImmX16: AddiuRxRxImmX16_base; + +// + // Format: ADDIU rx, pc, immediate MIPS16e // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) // To add a constant to the program counter. @@ -240,4 +263,7 @@ def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2), // Small immediates def : Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; -def : Mips16Pat<(MipsLo tglobaladdr:$in), (LiRxImmX16 tglobaladdr:$in)>; + + +def : Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), + (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 7741f9f9820..0f6adad1c48 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -2645,7 +2645,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVector &Ins = CLI.Ins; SDValue InChain = CLI.Chain; SDValue Callee = CLI.Callee; - SDValue CalleeSave = CLI.Callee; bool &isTailCall = CLI.IsTailCall; CallingConv::ID CallConv = CLI.CallConv; bool isVarArg = CLI.IsVarArg; @@ -2867,6 +2866,9 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } } + // T9 register operand. + SDValue T9; + // T9 should contain the address of the callee function if // -reloction-model=pic or it is an indirect call. if (IsPICCall || !GlobalOrExternal) { @@ -2874,7 +2876,11 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); InFlag = Chain.getValue(1); - Callee = DAG.getRegister(T9Reg, getPointerTy()); + + if (Subtarget->inMips16Mode()) + T9 = DAG.getRegister(T9Reg, getPointerTy()); + else + Callee = DAG.getRegister(T9Reg, getPointerTy()); } // Insert node "GP copy globalreg" before call to function. @@ -2902,7 +2908,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); SmallVector Ops; Ops.push_back(Chain); - Ops.push_back(Subtarget->inMips16Mode()? CalleeSave: Callee); + Ops.push_back(Callee); // Add argument registers to the end of the list so that they are // known live into the call. @@ -2910,8 +2916,10 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, Ops.push_back(DAG.getRegister(RegsToPass[i].first, RegsToPass[i].second.getValueType())); - if (Subtarget->inMips16Mode()) - Ops.push_back(Callee); + // Add T9 register operand. + if (T9.getNode()) + Ops.push_back(T9); + // Add a register mask operand representing the call-preserved registers. const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); diff --git a/test/CodeGen/Mips/helloworld.ll b/test/CodeGen/Mips/helloworld.ll new file mode 100644 index 00000000000..062ff7c9059 --- /dev/null +++ b/test/CodeGen/Mips/helloworld.ll @@ -0,0 +1,32 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1 +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2 +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR + + +@.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1 + +define i32 @main() nounwind { +entry: + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) + ret i32 0 + +; SR: .set mips16 # @main + +; SR: save $ra, [[FS:[0-9]+]] +; PE: li $[[T1:[0-9]+]], %hi(_gp_disp) +; PE: addiu $[[T2:[0-9]+]], $pc, %lo(_gp_disp) +; PE: sll $[[T3:[0-9]+]], $[[T1]], 16 +; C1: lw ${{[0-9]+}}, %got($.str)(${{[0-9]+}}) +; C2: lw ${{[0-9]+}}, %call16(printf)(${{[0-9]+}}) +; C1: addiu ${{[0-9]+}}, %lo($.str) +; C2: move $25, ${{[0-9]+}} +; C1: move $gp, ${{[0-9]+}} +; C1: jalr ${{[0-9]+}} +; SR: restore $ra, [[FS]] +; PE: li $2, 0 +; PE: jr $ra + +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/helloworld_call.ll b/test/CodeGen/Mips/helloworld_call.ll deleted file mode 100644 index 61c04460835..00000000000 --- a/test/CodeGen/Mips/helloworld_call.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 - -@.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1 - -define i32 @main() nounwind { -entry: - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) - ret i32 0 - -; 16: .set mips16 # @main - -; 16: move $gp, ${{[0-9]+}} -; 16: jalr ${{[0-9]+}} -; 16: li $2, 0 -} - -declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/helloworld_pe.ll b/test/CodeGen/Mips/helloworld_pe.ll deleted file mode 100644 index ba46662d526..00000000000 --- a/test/CodeGen/Mips/helloworld_pe.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 - -@.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1 - -define i32 @main() nounwind { -entry: - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) - ret i32 0 - -; 16: .set mips16 # @main - -; 16: li $[[T1:[0-9]+]], %hi(_gp_disp) -; 16: addiu $[[T2:[0-9]+]], $pc, %lo(_gp_disp) -; 16: sll $[[T3:[0-9]+]], $[[T1]], 16 -; 16: li $2, 0 -} - -declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/helloworld_sr.ll b/test/CodeGen/Mips/helloworld_sr.ll deleted file mode 100644 index 641ee274e02..00000000000 --- a/test/CodeGen/Mips/helloworld_sr.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 - -@.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1 - -define i32 @main() nounwind { -entry: - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) - ret i32 0 - -; 16: .set mips16 # @main - -; 16: save $ra, [[FS:[0-9]+]] -; 16: restore $ra, [[FS]] -} - -declare i32 @printf(i8*, ...)