From: Mark Brown <broonie@opensource.wolfsonmicro.com>
Date: Wed, 21 Oct 2009 17:17:58 +0000 (+0100)
Subject: ARM: S3C64XX: Set rate of crystal mux
X-Git-Tag: firefly_0821_release~11985^2~5^2
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e179ac0f4ea4f1e989fa754bada366f88fd81d27;p=firefly-linux-kernel-4.4.55.git

ARM: S3C64XX: Set rate of crystal mux

The current code assumes that the external clock mux will be set to
the crystal. Set this up explicitly within the clock API.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---

diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 9745852261e0..6ffa21eb1b91 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -677,6 +677,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
 
 	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 
+	/* For now assume the mux always selects the crystal */
+	clk_ext_xtal_mux.parent = xtal_clk;
+
 	epll = s3c6400_get_epll(xtal);
 	mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
 	apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));