From: dkl <dkl@rock-chips.com>
Date: Tue, 10 Feb 2015 03:01:25 +0000 (+0800)
Subject: dts: rk3126\rk3126b: modify VIO clocks to slove VIO idle fail problem
X-Git-Tag: firefly_0821_release~4263^2~52
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e57670a8e14e14601ff6b399efbff7063791f7e2;p=firefly-linux-kernel-4.4.55.git

dts: rk3126\rk3126b: modify VIO clocks to slove VIO idle fail problem

In rk3126, when aclk_vio0\aclk_vio1\hclk_vio were reparented from the
default parent gpll_div2 to gpll in clk_init, the temporary rates
are too high and may lead to failture in VIO idle_request later.
To slove this problem, VIO clocks are modified to auto select parent
and consider the order of reparent and set_div when set_rate.

Signed-off-by: dkl <dkl@rock-chips.com>
---

diff --git a/arch/arm/boot/dts/rk3126.dtsi b/arch/arm/boot/dts/rk3126.dtsi
index c4f7b8263aca..bd0973d3067c 100644
--- a/arch/arm/boot/dts/rk3126.dtsi
+++ b/arch/arm/boot/dts/rk3126.dtsi
@@ -8,6 +8,19 @@
 	clocks = <&dummy>;
 };
 
+
+&aclk_vio0_pre_div {
+	rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
+};
+
+&aclk_vio1_pre_div {
+        rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
+};
+
+&hclk_vio_pre_div {
+        rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
+};
+
 &rockchip_clocks_init {
 	rockchip,clocks-init-parent =
 		<&clk_core &clk_apll>, <&aclk_cpu &clk_gpll>,
@@ -15,8 +28,7 @@
 		<&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
 		<&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 		<&clk_vepu &clk_gpll>, <&clk_vdpu &clk_gpll>,
-		<&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll>,
-		<&aclk_vio1_pre &clk_gpll>, <&hclk_vio_pre &clk_gpll>,
+		<&clk_hevc_core &clk_gpll>,
 		<&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll>,
 		<&clk_cif_pll &clk_gpll>, <&dclk_ebc &clk_gpll>,
 		<&clk_emmc &clk_gpll>, <&clk_sdio &clk_gpll>,
@@ -29,4 +41,4 @@
 	/* sdi: 0: from io, 1: from acodec */
 	sdi_source = <1>;
 	status = "okay";
-};
\ No newline at end of file
+};