From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Mon, 5 Jun 2017 02:20:29 +0000 (+0800)
Subject: ASoC: rockchip: i2s: fixup clk div
X-Git-Tag: release-20171130_firefly~4^2~433
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e5c89b56c95ef08a87d17c47f3798f3745090ad3;p=firefly-linux-kernel-4.4.55.git

ASoC: rockchip: i2s: fixup clk div

we found mclk maybe not precise as required because of PLL,
but it still can be used and no side effect. for example, if we
require mclk 11289600, but get 11289598, it doesn't matter.
so using DIV_ROUND_CLOSEST to fix it.

Change-Id: If8453a7a08b319da81b07d572b02247bd7e7bd27
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
---

diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
index d7aa635e3693..2c7e5ccca2dc 100644
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -282,10 +282,10 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 	if (i2s->is_master_mode) {
 		mclk_rate = clk_get_rate(i2s->mclk);
 		bclk_rate = i2s->bclk_fs * params_rate(params);
-		if (bclk_rate && mclk_rate % bclk_rate)
+		if (!bclk_rate)
 			return -EINVAL;
 
-		div_bclk = mclk_rate / bclk_rate;
+		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
 		div_lrck = bclk_rate / params_rate(params);
 		regmap_update_bits(i2s->regmap, I2S_CKR,
 				   I2S_CKR_MDIV_MASK,