From: Craig Topper Date: Mon, 30 Dec 2013 19:16:48 +0000 (+0000) Subject: Remove special form of AddRegFrm used by FP instructions. These instructions can... X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e6d2dce7abe723744b4889d013b4f5751504b8e4;p=oota-llvm.git Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198238 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c index 4b97678d0c7..7b6b49f6f4a 100644 --- a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c +++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c @@ -1528,9 +1528,6 @@ static int readOpcodeModifier(struct InternalInstruction* insn) { case MODIFIER_OPCODE: insn->opcodeModifier = insn->opcode - insn->spec->modifierBase; return 0; - case MODIFIER_MODRM: - insn->opcodeModifier = insn->modRM - insn->spec->modifierBase; - return 0; } } diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h b/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h index 7afe088c6bd..e8482c68448 100644 --- a/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h +++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h @@ -526,8 +526,7 @@ struct OperandSpecifier { #define MODIFIER_TYPES \ ENUM_ENTRY(MODIFIER_NONE) \ - ENUM_ENTRY(MODIFIER_OPCODE) \ - ENUM_ENTRY(MODIFIER_MODRM) + ENUM_ENTRY(MODIFIER_OPCODE) #define ENUM_ENTRY(n) n, typedef enum { diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 7c3788865c1..ded44eea06a 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -218,37 +218,37 @@ defm DIV : FPBinary; defm DIVR: FPBinary; } -class FPST0rInst o, string asm> - : FPI, D8; -class FPrST0Inst o, string asm> - : FPI, DC; -class FPrST0PInst o, string asm> - : FPI, DE; +class FPST0rInst + : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; +class FPrST0Inst + : FPI<0xDC, fp, (outs), (ins RST:$op), asm>; +class FPrST0PInst + : FPI<0xDE, fp, (outs), (ins RST:$op), asm>; // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, // we have to put some 'r's in and take them out of weird places. -def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">; -def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, st(0)}">; -def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">; -def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">; -def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, st(0)}">; -def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">; -def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">; -def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; -def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">; -def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">; -def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, st(0)}">; -def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">; -def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">; -def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; -def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">; -def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">; -def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; -def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">; - -def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">; -def COMP_FST0r : FPST0rInst <0xD8, "fcomp\t$op">; +def ADD_FST0r : FPST0rInst ; +def ADD_FrST0 : FPrST0Inst ; +def ADD_FPrST0 : FPrST0PInst; +def SUBR_FST0r : FPST0rInst ; +def SUB_FrST0 : FPrST0Inst ; +def SUB_FPrST0 : FPrST0PInst; +def SUB_FST0r : FPST0rInst ; +def SUBR_FrST0 : FPrST0Inst ; +def SUBR_FPrST0 : FPrST0PInst; +def MUL_FST0r : FPST0rInst ; +def MUL_FrST0 : FPrST0Inst ; +def MUL_FPrST0 : FPrST0PInst; +def DIVR_FST0r : FPST0rInst ; +def DIV_FrST0 : FPrST0Inst ; +def DIV_FPrST0 : FPrST0PInst; +def DIV_FST0r : FPST0rInst ; +def DIVR_FrST0 : FPrST0Inst ; +def DIVR_FPrST0 : FPrST0PInst; + +def COM_FST0r : FPST0rInst ; +def COMP_FST0r : FPST0rInst ; // Unary operations. multiclass FPUnary opcode, string asmstring> { @@ -336,22 +336,22 @@ defm CMOVNP : FPCMov; let Predicates = [HasCMov] in { // These are not factored because there's no clean way to pass DA/DB. -def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), - "fcmovb\t{$op, %st(0)|st(0), $op}">, DA; -def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), - "fcmovbe\t{$op, %st(0)|st(0), $op}">, DA; -def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), - "fcmove\t{$op, %st(0)|st(0), $op}">, DA; -def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), - "fcmovu\t{$op, %st(0)|st(0), $op}">, DA; -def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), - "fcmovnb\t{$op, %st(0)|st(0), $op}">, DB; -def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), - "fcmovnbe\t{$op, %st(0)|st(0), $op}">, DB; -def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), - "fcmovne\t{$op, %st(0)|st(0), $op}">, DB; -def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), - "fcmovnu\t{$op, %st(0)|st(0), $op}">, DB; +def CMOVB_F : FPI<0xDA, MRM0r, (outs RST:$op), (ins), + "fcmovb\t{$op, %st(0)|st(0), $op}">; +def CMOVBE_F : FPI<0xDA, MRM2r, (outs RST:$op), (ins), + "fcmovbe\t{$op, %st(0)|st(0), $op}">; +def CMOVE_F : FPI<0xDA, MRM1r, (outs RST:$op), (ins), + "fcmove\t{$op, %st(0)|st(0), $op}">; +def CMOVP_F : FPI<0xDA, MRM3r, (outs RST:$op), (ins), + "fcmovu\t{$op, %st(0)|st(0), $op}">; +def CMOVNB_F : FPI<0xDB, MRM0r, (outs RST:$op), (ins), + "fcmovnb\t{$op, %st(0)|st(0), $op}">; +def CMOVNBE_F: FPI<0xDB, MRM2r, (outs RST:$op), (ins), + "fcmovnbe\t{$op, %st(0)|st(0), $op}">; +def CMOVNE_F : FPI<0xDB, MRM1r, (outs RST:$op), (ins), + "fcmovne\t{$op, %st(0)|st(0), $op}">; +def CMOVNP_F : FPI<0xDB, MRM3r, (outs RST:$op), (ins), + "fcmovnu\t{$op, %st(0)|st(0), $op}">; } // Predicates = [HasCMov] // Floating point loads & stores. @@ -492,14 +492,10 @@ def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), // FP Stack manipulation instructions. let SchedRW = [WriteMove] in { -def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op", - IIC_FLD>, D9; -def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op", - IIC_FST>, DD; -def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op", - IIC_FST>, DD; -def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op", - IIC_FXCH>, D9; +def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>; +def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>; +def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>; +def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>; } // Floating point constant loads. @@ -546,31 +542,26 @@ def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, } let Defs = [FPSW], Uses = [ST0] in { -def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) - (outs), (ins RST:$reg), - "fucom\t$reg", IIC_FUCOM>, DD; -def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop - (outs), (ins RST:$reg), - "fucomp\t$reg", IIC_FUCOM>, DD; +def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) + (outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>; +def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop + (outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>; def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop - (outs), (ins), - "fucompp", IIC_FUCOM>, DA; + (outs), (ins), "fucompp", IIC_FUCOM>, DA; } let Defs = [EFLAGS, FPSW], Uses = [ST0] in { -def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) - (outs), (ins RST:$reg), - "fucomi\t$reg", IIC_FUCOMI>, DB; -def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop - (outs), (ins RST:$reg), - "fucompi\t$reg", IIC_FUCOMI>, DF; +def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) + (outs), (ins RST:$reg), "fucomi\t$reg", IIC_FUCOMI>; +def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop + (outs), (ins RST:$reg), "fucompi\t$reg", IIC_FUCOMI>; } let Defs = [EFLAGS, FPSW] in { -def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg), - "fcomi\t$reg", IIC_FCOMI>, DB; -def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg), - "fcompi\t$reg", IIC_FCOMI>, DF; +def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), + "fcomi\t$reg", IIC_FCOMI>; +def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), + "fcompi\t$reg", IIC_FCOMI>; } } // SchedRW @@ -594,8 +585,8 @@ def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] let SchedRW = [WriteMicrocoded] in { let Defs = [FPSW] in def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", [], IIC_FNINIT>, DB; -def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg), - "ffree\t$reg", IIC_FFREE>, DD; +def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), + "ffree\t$reg", IIC_FFREE>; // Clear exceptions let Defs = [FPSW] in diff --git a/utils/TableGen/X86ModRMFilters.cpp b/utils/TableGen/X86ModRMFilters.cpp index a311603df9d..1641613aa32 100644 --- a/utils/TableGen/X86ModRMFilters.cpp +++ b/utils/TableGen/X86ModRMFilters.cpp @@ -17,8 +17,6 @@ void DumbFilter::anchor() { } void ModFilter::anchor() { } -void AddRegEscapeFilter::anchor() { } - void ExtendedFilter::anchor() { } void ExactFilter::anchor() { } diff --git a/utils/TableGen/X86ModRMFilters.h b/utils/TableGen/X86ModRMFilters.h index 5ab1a48846b..049cfc1d3b5 100644 --- a/utils/TableGen/X86ModRMFilters.h +++ b/utils/TableGen/X86ModRMFilters.h @@ -84,26 +84,6 @@ public: } }; -/// AddRegEscapeFilter - Some escape opcodes have one of the register operands -/// added to the ModR/M byte, meaning that a range of eight ModR/M values -/// maps to a single instruction. Such instructions require the ModR/M byte -/// to fall between 0xc0 and 0xff. -class AddRegEscapeFilter : public ModRMFilter { - virtual void anchor(); - uint8_t ModRM; -public: - /// Constructor - /// - /// \param modRM The value of the ModR/M byte when the register operand - /// refers to the first register in the register set. - AddRegEscapeFilter(uint8_t modRM) : ModRM(modRM) { - } - - bool accepts(uint8_t modRM) const { - return (modRM >= ModRM && modRM < ModRM + 8); - } -}; - /// ExtendedFilter - Extended opcodes are classified based on the value of the /// mod field [bits 7-6] and the value of the nnn field [bits 5-3]. class ExtendedFilter : public ModRMFilter { diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 1eb579df3f5..6a2a0d504f6 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -1075,14 +1075,9 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { case X86Local::DE: case X86Local::DF: assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode"); + assert(Form == X86Local::RawFrm); opcodeType = ONEBYTE; - if (Form == X86Local::AddRegFrm) { - Spec->modifierType = MODIFIER_MODRM; - Spec->modifierBase = Opcode; - filter = new AddRegEscapeFilter(Opcode); - } else { - filter = new ExactFilter(Opcode); - } + filter = new ExactFilter(Opcode); opcodeToSet = 0xd8 + (Prefix - X86Local::D8); break; case X86Local::REP: @@ -1130,6 +1125,16 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { switch (Form) { default: llvm_unreachable("Unhandled escape opcode form"); + case X86Local::MRM0r: + case X86Local::MRM1r: + case X86Local::MRM2r: + case X86Local::MRM3r: + case X86Local::MRM4r: + case X86Local::MRM5r: + case X86Local::MRM6r: + case X86Local::MRM7r: + filter = new ExtendedFilter(true, Form - X86Local::MRM0r); + break; case X86Local::MRM0m: case X86Local::MRM1m: case X86Local::MRM2m: @@ -1157,31 +1162,22 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { assert(filter && "Filter not set"); if (Form == X86Local::AddRegFrm) { - if(Spec->modifierType != MODIFIER_MODRM) { - assert(opcodeToSet < 0xf9 && - "Not enough room for all ADDREG_FRM operands"); - - uint8_t currentOpcode; - - for (currentOpcode = opcodeToSet; - currentOpcode < opcodeToSet + 8; - ++currentOpcode) - tables.setTableFields(opcodeType, - insnContext(), - currentOpcode, - *filter, - UID, Is32Bit, IgnoresVEX_L); - - Spec->modifierType = MODIFIER_OPCODE; - Spec->modifierBase = opcodeToSet; - } else { - // modifierBase was set where MODIFIER_MODRM was set + assert(opcodeToSet < 0xf9 && + "Not enough room for all ADDREG_FRM operands"); + + uint8_t currentOpcode; + + for (currentOpcode = opcodeToSet; + currentOpcode < opcodeToSet + 8; + ++currentOpcode) tables.setTableFields(opcodeType, insnContext(), - opcodeToSet, + currentOpcode, *filter, UID, Is32Bit, IgnoresVEX_L); - } + + Spec->modifierType = MODIFIER_OPCODE; + Spec->modifierBase = opcodeToSet; } else { tables.setTableFields(opcodeType, insnContext(), @@ -1341,6 +1337,7 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString OperandEncoding RecognizableInstr::rmRegisterEncodingFromString (const std::string &s, bool hasOpSizePrefix) { + ENCODING("RST", ENCODING_I) ENCODING("GR16", ENCODING_RM) ENCODING("GR32", ENCODING_RM) ENCODING("GR32orGR64", ENCODING_RM) @@ -1493,7 +1490,6 @@ OperandEncoding RecognizableInstr::relocationEncodingFromString OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString (const std::string &s, bool hasOpSizePrefix) { - ENCODING("RST", ENCODING_I) ENCODING("GR32", ENCODING_Rv) ENCODING("GR64", ENCODING_RO) ENCODING("GR16", ENCODING_Rv)