From: Misha Brukman <brukman+llvm@gmail.com>
Date: Tue, 27 Jul 2004 17:15:32 +0000 (+0000)
Subject: LR is a 32-bit int reg
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e862f306fb630f0301bb04d8a5a2868db4f7fcd6;p=oota-llvm.git

LR is a 32-bit int reg


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15273 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 8324b9439d0..28bfa362eb6 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -79,11 +79,11 @@ def GPRC :
   RegisterClass<i32, 4, 
     [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, 
      R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
-     R16, R15, R14, R13, R0, R1]>
+     R16, R15, R14, R13, R0, R1, LR]>
 {
   let Methods = [{
     iterator allocation_order_end(MachineFunction &MF) const {
-      return end()-2;
+      return end()-3;
     }
   }];
 }