From: Colin LeMahieu <colinl@codeaurora.org>
Date: Wed, 31 Dec 2014 15:57:38 +0000 (+0000)
Subject: [Hexagon] Changing an llvm_unreachable to an assertion and returning 0.  Relocations... 
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e883ee78f2e231d937d274256e69841bec00188a;p=oota-llvm.git

[Hexagon] Changing an llvm_unreachable to an assertion and returning 0.  Relocations aren't implemented yet but we don't need to abort for this in release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225043 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
index 4471977ab49..830be55431d 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
@@ -71,7 +71,8 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
     return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
   if (MO.isImm())
     return static_cast<unsigned>(MO.getImm());
-  llvm_unreachable("Only Immediates and Registers implemented right now");
+  assert(false && "Only Immediates and Registers implemented right now");
+  return 0;
 }
 
 MCSubtargetInfo const &HexagonMCCodeEmitter::getSubtargetInfo() const {