From: Chris Lattner Date: Sat, 14 May 2005 07:25:05 +0000 (+0000) Subject: Use the general mechanism for creating multi-value nodes instead of using X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e89083a9300dc463e3b79eabe2b9913d85338d28;p=oota-llvm.git Use the general mechanism for creating multi-value nodes instead of using special case hacks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22014 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 680b2ce9bca..d0de8c9b819 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1056,8 +1056,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Ops.push_back(LegalizeOp(Node->getOperand(i))); Changed |= Ops.back() != Node->getOperand(i); } - if (Changed) - Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); + if (Changed) { + std::vector VTs(Node->value_begin(), Node->value_end()); + Result = DAG.getNode(Node->getOpcode(), VTs, Ops); + } // Since these produce multiple values, make sure to remember that we // legalized all of them. @@ -1784,32 +1786,34 @@ ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, ExpandOp(RHS, RHSL, RHSH); // FIXME: this should be moved to the dag combiner someday. - if (NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS) - if (LHSL.getValueType() == MVT::i32) { - SDOperand LowEl; - if (ConstantSDNode *C = dyn_cast(LHSL)) - if (C->getValue() == 0) - LowEl = RHSL; - if (ConstantSDNode *C = dyn_cast(RHSL)) - if (C->getValue() == 0) - LowEl = LHSL; - if (LowEl.Val) { - // Turn this into an add/sub of the high part only. - SDOperand HiEl = - DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB, - LowEl.getValueType(), LHSH, RHSH); - Lo = LowEl; - Hi = HiEl; - return; - } + assert(NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS); + if (LHSL.getValueType() == MVT::i32) { + SDOperand LowEl; + if (ConstantSDNode *C = dyn_cast(LHSL)) + if (C->getValue() == 0) + LowEl = RHSL; + if (ConstantSDNode *C = dyn_cast(RHSL)) + if (C->getValue() == 0) + LowEl = LHSL; + if (LowEl.Val) { + // Turn this into an add/sub of the high part only. + SDOperand HiEl = + DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB, + LowEl.getValueType(), LHSH, RHSH); + Lo = LowEl; + Hi = HiEl; + return; } + } std::vector Ops; Ops.push_back(LHSL); Ops.push_back(LHSH); Ops.push_back(RHSL); Ops.push_back(RHSH); - Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops); + + std::vector VTs(2, LHSL.getValueType()); + Lo = DAG.getNode(NodeOp, VTs, Ops); Hi = Lo.getValue(1); } @@ -1824,7 +1828,11 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, Ops.push_back(LHSL); Ops.push_back(LHSH); Ops.push_back(Amt); - Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops); + std::vector VTs; + VTs.push_back(LHSL.getValueType()); + VTs.push_back(LHSH.getValueType()); + VTs.push_back(Amt.getValueType()); + Lo = DAG.getNode(NodeOp, VTs, Ops); Hi = Lo.getValue(1); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 6064598ff2b..165b3c92f18 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1347,44 +1347,20 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, else return N1; // Never-taken branch break; - // FIXME: figure out how to safely handle things like - // int foo(int x) { return 1 << (x & 255); } - // int bar() { return foo(256); } -#if 0 - case ISD::SRA_PARTS: - case ISD::SRL_PARTS: - case ISD::SHL_PARTS: - if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && - cast(N3)->getExtraValueType() != MVT::i1) - return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); - else if (N3.getOpcode() == ISD::AND) - if (ConstantSDNode *AndRHS = dyn_cast(N3.getOperand(1))) { - // If the and is only masking out bits that cannot effect the shift, - // eliminate the and. - unsigned NumBits = MVT::getSizeInBits(VT)*2; - if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) - return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); - } - break; -#endif } SDNode *N = new SDNode(Opcode, N1, N2, N3); switch (Opcode) { + case ISD::SRA_PARTS: + case ISD::SRL_PARTS: + case ISD::SHL_PARTS: + assert(0 && "Should not get here!"); default: N->setValueTypes(VT); break; case ISD::DYNAMIC_STACKALLOC: // DYNAMIC_STACKALLOC produces pointer and chain N->setValueTypes(VT, MVT::Other); break; - - case ISD::SRA_PARTS: - case ISD::SRL_PARTS: - case ISD::SHL_PARTS: { - std::vector V(N->getNumOperands()-1, VT); - N->setValueTypes(V); - break; - } } // FIXME: memoize NODES @@ -1428,6 +1404,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, ConstantSDNode *N1C = dyn_cast(Ops[1].Val); switch (Opcode) { + case ISD::ADD_PARTS: + case ISD::SUB_PARTS: + assert(0 && "Shouldn't be here, should set multiple retvals"); default: break; case ISD::BRCONDTWOWAY: if (N1C) @@ -1440,12 +1419,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, // FIXME: MEMOIZE!! SDNode *N = new SDNode(Opcode, Ops); - if (Opcode != ISD::ADD_PARTS && Opcode != ISD::SUB_PARTS) { - N->setValueTypes(VT); - } else { - std::vector V(N->getNumOperands()/2, VT); - N->setValueTypes(V); - } + N->setValueTypes(VT); AllNodes.push_back(N); return SDOperand(N, 0); } @@ -1456,6 +1430,28 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, if (ResultTys.size() == 1) return getNode(Opcode, ResultTys[0], Ops); + // FIXME: figure out how to safely handle things like + // int foo(int x) { return 1 << (x & 255); } + // int bar() { return foo(256); } +#if 0 + switch (Opcode) { + case ISD::SRA_PARTS: + case ISD::SRL_PARTS: + case ISD::SHL_PARTS: + if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && + cast(N3)->getExtraValueType() != MVT::i1) + return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); + else if (N3.getOpcode() == ISD::AND) + if (ConstantSDNode *AndRHS = dyn_cast(N3.getOperand(1))) { + // If the and is only masking out bits that cannot effect the shift, + // eliminate the and. + unsigned NumBits = MVT::getSizeInBits(VT)*2; + if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) + return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); + } + break; + } +#endif // Memoize the node. SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys,