From: hcy <hcy@rock-chips.com>
Date: Fri, 28 Sep 2012 08:41:23 +0000 (+0800)
Subject: update DPLL rate after change DDR frequency
X-Git-Tag: firefly_0821_release~8513
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e8ca677ea2819455d6c52ca64893356bbd0d66c1;p=firefly-linux-kernel-4.4.55.git

update DPLL rate after change DDR frequency
---

diff --git a/arch/arm/mach-rk2928/ddr.c b/arch/arm/mach-rk2928/ddr.c
index 9acb76b5c726..05dbd8f7ce13 100755
--- a/arch/arm/mach-rk2928/ddr.c
+++ b/arch/arm/mach-rk2928/ddr.c
@@ -2242,6 +2242,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
                                                                     (ddr_get_cap()>>20));
     ddr_adjust_config(mem_type);
     value=ddr_change_freq(freq);
+    clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
     ddr_print("init success!!! freq=%dMHz\n", value);
 
     calStatusLeft = pPHY_Reg->PHY_REG60;