From: Mon P Wang Date: Tue, 9 Dec 2008 05:46:39 +0000 (+0000) Subject: Fix getNode to allow a vector for the shift amount for shifts of vectors. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=e9f1015d1f184a51aaadfd03be0846bd5e7d08a2;p=oota-llvm.git Fix getNode to allow a vector for the shift amount for shifts of vectors. Fix the shift amount when unrolling a vector shift into scalar shifts. Fix problem in getShuffleScalarElt where it assumes that the input of a bit convert must be a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60740 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/docs/LangRef.html b/docs/LangRef.html index 74027cebe6d..48b619a74ba 100644 --- a/docs/LangRef.html +++ b/docs/LangRef.html @@ -2591,6 +2591,7 @@ equal to or larger than the number of bits in op1, the result is undefi <result> = shl i32 4, 2 ; yields {i32}: 16 <result> = shl i32 1, 10 ; yields {i32}: 1024 <result> = shl i32 1, 32 ; undefined + <result> = shl <2 x i32> < i32 1, i32 1>, < i32 1, i32 2> ; yields: result=<2 x i32> < i32 2, i32 4> @@ -2624,6 +2625,7 @@ the number of bits in op1, the result is undefined.

<result> = lshr i8 4, 3 ; yields {i8}:result = 0 <result> = lshr i8 -2, 1 ; yields {i8}:result = 0x7FFFFFFF <result> = lshr i32 1, 32 ; undefined + <result> = lshr <2 x i32> < i32 -2, i32 4>, < i32 1, i32 2> ; yields: result=<2 x i32> < i32 0x7FFFFFFF, i32 1> @@ -2659,6 +2661,7 @@ larger than the number of bits in op1, the result is undefined. <result> = ashr i8 4, 3 ; yields {i8}:result = 0 <result> = ashr i8 -2, 1 ; yields {i8}:result = -1 <result> = ashr i32 1, 32 ; undefined + <result> = ashr <2 x i32> < i32 -2, i32 4>, < i32 1, i32 3> ; yields: result=<2 x i32> < i32 -1, i32 0> diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index d61d6ca6fdf..445d32ff1b8 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -297,6 +297,9 @@ private: SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); + + // Returns the legalized (truncated or extended) shift amount. + SDValue LegalizeShiftAmount(SDValue ShiftAmt); }; } @@ -786,8 +789,19 @@ SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { Operands[j] = Operand; } } - Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, - &Operands[0], Operands.size())); + + switch (Op.getOpcode()) { + default: + Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, + &Operands[0], Operands.size())); + break; + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0], + LegalizeShiftAmount(Operands[1]))); + break; + } } return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); @@ -850,6 +864,17 @@ PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) { PseudoSourceValue::getFixedStack(SPFI), 0); } +SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) { + if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType())) + return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); + + if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) + return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); + + return ShiftAmt; +} + + /// LegalizeOp - We know that the specified value has a legal type, and /// that its operands are legal. Now ensure that the operation itself /// is legal, recursively ensuring that the operands' operations remain @@ -3094,11 +3119,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { Node->getOpcode() == ISD::SRL || Node->getOpcode() == ISD::SRA) && !Node->getValueType(0).isVector()) { - if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType())) - Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2); - else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType())) - Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2); - } + Tmp2 = LegalizeShiftAmount(Tmp2); + } Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 6fc2a67e296..34f0ccac47d 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2066,7 +2066,8 @@ SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { if (V.getOpcode() == ISD::BIT_CONVERT) { V = V.getOperand(0); - if (V.getValueType().getVectorNumElements() != NumElems) + MVT VVT = V.getValueType(); + if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) return SDValue(); } if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) @@ -2418,7 +2419,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, "Shift operators return type must be the same as their first arg"); assert(VT.isInteger() && N2.getValueType().isInteger() && "Shifts only work on integers"); - assert(N2.getValueType() == TLI.getShiftAmountTy() && + assert((N2.getValueType() == TLI.getShiftAmountTy() || + (N2.getValueType().isVector() && N2.getValueType().isInteger())) && "Wrong type for shift amount"); // Always fold shifts of i1 values so the code generator doesn't need to diff --git a/test/CodeGen/X86/vshift_split.ll b/test/CodeGen/X86/vshift_split.ll new file mode 100644 index 00000000000..8f485ddd9a6 --- /dev/null +++ b/test/CodeGen/X86/vshift_split.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc + +; Example that requires splitting and expanding a vector shift. +define <2 x i64> @update(<2 x i64> %val) nounwind readnone { +entry: + %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1] + ret <2 x i64> %shr +}