From: Finley Xiao Date: Thu, 6 Apr 2017 03:40:01 +0000 (+0800) Subject: clk: rockchip: rk3288: add ddrc clock support X-Git-Tag: release-20171130_firefly~4^2~686 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ed39592cfa8521cf1b91160ad4946a535af99a1e;p=firefly-linux-kernel-4.4.55.git clk: rockchip: rk3288: add ddrc clock support Add a ddrc clock into clk branches, so we can do ddr frequency scaling on rk3288 platform in future. Change-Id: Ia6c93e5ce82fa30475eddf051bc9ea2512b0cc07 Signed-off-by: Finley Xiao --- diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index c9c32f0acb07..6c2e24b0e7b7 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -308,6 +308,9 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(0), 8, GFLAGS), GATE(0, "gpll_ddr", "gpll", 0, RK3288_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0, + RK3288_CLKSEL_CON(26), 2, 1, 0, 0, + ROCKCHIP_DDRCLK_SIP), COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),