From: Antti Hatala <ahatala@nvidia.com>
Date: Thu, 26 Aug 2010 11:16:58 +0000 (-0700)
Subject: [ARM] tegra: stingray: remove clock and powergate hacks
X-Git-Tag: firefly_0821_release~9834^2~578
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=edd4c87e4dbfdc88c304de54e6c44114dc80b2ea;p=firefly-linux-kernel-4.4.55.git

[ARM] tegra: stingray: remove clock and powergate hacks

Remove unpowergating of 3d on board init to let the host1x driver
handle it.

Remove enabling hw module clocks on board init for modules behind
host1x.

Keep pll_m clock force-enabled for now as the pll clk disable code
path is not fully functional.

Change-Id: I4721d117b736a591b3cf3ee9f8967b88212f88b8
Signed-off-by: Erik Gilling <konkers@android.com>
---

diff --git a/arch/arm/mach-tegra/board-stingray.c b/arch/arm/mach-tegra/board-stingray.c
index 6a78a9b0f7b4..a7343b62f167 100644
--- a/arch/arm/mach-tegra/board-stingray.c
+++ b/arch/arm/mach-tegra/board-stingray.c
@@ -640,13 +640,8 @@ static __initdata struct tegra_clk_init_table stingray_clk_init_table[] = {
 	{ "uartb",	"clk_m",	26000000,	true},
 	{ "uartc",	"pll_m",	600000000,	false},
 	/*{ "emc",	"pll_p",	0,		true},
-	{ "pll_m",	NULL,		600000000,	true},
 	{ "emc",	"pll_m",	600000000,	false},*/
-	{ "host1x",	"pll_m",	150000000,	true},
-	{ "2d",		"pll_m",	300000000,	true},
-	{ "3d",		"pll_m",	300000000,	true},
-	{ "epp",	"pll_m",	100000000,	true},
-	{ "vi",		"pll_m",	100000000,	true},
+	{ "pll_m",	NULL,		600000000,	true},
 	{ "pll_a",	NULL,		24000000,	false},
 	{ "pll_a_out0",	NULL,		24000000,	false},
 	{ "i2s1",	"pll_a_out0",	24000000,	false},
@@ -981,15 +976,6 @@ static void __init tegra_stingray_init(void)
 	nvmap_add_carveout_heap(TEGRA_IRAM_BASE, TEGRA_IRAM_SIZE, "iram",
 				NVMEM_HEAP_CARVEOUT_IRAM);
 
-	clk = clk_get_sys("3d", NULL);
-	tegra_periph_reset_assert(clk);
-	writel(0x101, IO_ADDRESS(TEGRA_PMC_BASE) + 0x30);
-	clk_enable(clk);
-	udelay(10);
-	writel(1 << 1, IO_ADDRESS(TEGRA_PMC_BASE) + 0x34);
-	tegra_periph_reset_deassert(clk);
-	clk_put(clk);
-
 	init_das();
 	tegra_i2s_device1.dev.platform_data = &tegra_audio_pdata;
 	cpcap_device_register(&cpcap_audio_device);