From: Evan Cheng Date: Fri, 25 Apr 2008 07:56:45 +0000 (+0000) Subject: MMX argument passing fixes: X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ee472b10814b00eed86f2f8cdab0cbdab431d627;p=oota-llvm.git MMX argument passing fixes: On Darwin / Linux x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2]. On Darwin / Linux x86-32, v1i64 values are passed in memory. On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7]. On Darwin x86-64, v1i64 values are passed in 64-bit GPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50257 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td index 8a580df6ae6..b2a02e4a387 100644 --- a/lib/Target/X86/X86CallingConv.td +++ b/lib/Target/X86/X86CallingConv.td @@ -133,12 +133,20 @@ def CC_X86_64_C : CallingConv<[ // The first 8 FP/Vector arguments are passed in XMM registers. CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], - CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>, - - // The first 8 MMX vector arguments are passed in GPRs. - CCIfType<[v8i8, v4i16, v2i32, v1i64], - CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, - + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>, + + // The first 8 MMX (except for v1i64) vector arguments are passed in XMM + // registers on Darwin. + CCIfType<[v8i8, v4i16, v2i32], + CCIfSubtarget<"isTargetDarwin()", + CCIfSubtarget<"hasSSE2()", + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>, + + // The first 8 v1i64 vector arguments are passed in GPRs on Darwin. + CCIfType<[v1i64], + CCIfSubtarget<"isTargetDarwin()", + CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>, + // Integer/FP values get stored in stack slots that are 8 bytes in size and // 8-byte aligned if there are no more registers to hold them. CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, @@ -211,12 +219,19 @@ def CC_X86_64_TailCall : CallingConv<[ // The first 8 FP/Vector arguments are passed in XMM registers. CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], - CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>, - - // The first 8 MMX vector arguments are passed in GPRs. - CCIfType<[v8i8, v4i16, v2i32, v1i64], - CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>, - + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>, + + // The first 8 MMX (except for v1i64) vector arguments are passed in XMM + // registers on Darwin. + CCIfType<[v8i8, v4i16, v2i32], + CCIfSubtarget<"isTargetDarwin()", + CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, + + // The first 8 v1i64 vector arguments are passed in GPRs on Darwin. + CCIfType<[v1i64], + CCIfSubtarget<"isTargetDarwin()", + CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>, + // Integer/FP values get stored in stack slots that are 8 bytes in size and // 8-byte aligned if there are no more registers to hold them. CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, @@ -242,9 +257,15 @@ def CC_X86_32_Common : CallingConv<[ // The first 3 float or double arguments, if marked 'inreg' and if the call // is not a vararg call and if SSE2 is available, are passed in SSE registers. - CCIfNotVarArg>>>>, + // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx + // registers if the call is not a vararg call. + CCIfNotVarArg>>, + // Integer/Float values get stored in stack slots that are 4 bytes in // size and 4-byte aligned. CCIfType<[i32, f32], CCAssignToStack<4, 4>>, @@ -264,8 +285,7 @@ def CC_X86_32_Common : CallingConv<[ // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are // passed in the parameter area. - CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>> -]>; + CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>; def CC_X86_32_C : CallingConv<[ // Promote i8/i16 arguments to i32. diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index a0fd3d90c5e..38949601f6a 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1207,13 +1207,25 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { RC = X86::FR32RegisterClass; else if (RegVT == MVT::f64) RC = X86::FR64RegisterClass; - else { - assert(MVT::isVector(RegVT)); - if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) { - RC = X86::GR64RegisterClass; // MMX values are passed in GPRs. - RegVT = MVT::i64; - } else - RC = X86::VR128RegisterClass; + else if (MVT::isVector(RegVT) && MVT::getSizeInBits(RegVT) == 128) + RC = X86::VR128RegisterClass; + else if (MVT::isVector(RegVT)) { + assert(MVT::getSizeInBits(RegVT) == 64); + if (!Is64Bit) + RC = X86::VR64RegisterClass; // MMX values are passed in MMXs. + else { + // Darwin calling convention passes MMX values in either GPRs or + // XMMs in x86-64. Other targets pass them in memory. + if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) { + RC = X86::VR128RegisterClass; // MMX values are passed in XMMs. + RegVT = MVT::v2i64; + } else { + RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs. + RegVT = MVT::i64; + } + } + } else { + assert(0 && "Unknown argument type!"); } unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); diff --git a/test/CodeGen/X86/mmx-arg-passing.ll b/test/CodeGen/X86/mmx-arg-passing.ll new file mode 100644 index 00000000000..232a98a8959 --- /dev/null +++ b/test/CodeGen/X86/mmx-arg-passing.ll @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+mmx | grep mm0 | count 3 +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+mmx | grep esp | count 1 +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep xmm0 +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep rdi +; +; On Darwin x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2]. +; On Darwin x86-32, v1i64 values are passed in memory. +; On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7]. +; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs. + +@u1 = external global <8 x i8> + +define void @t1(<8 x i8> %v1) nounwind { + store <8 x i8> %v1, <8 x i8>* @u1, align 8 + ret void +} + +@u2 = external global <1 x i64> + +define void @t2(<1 x i64> %v1) nounwind { + store <1 x i64> %v1, <1 x i64>* @u2, align 8 + ret void +}