From: Akira Hatanaka Date: Mon, 19 Dec 2011 19:44:09 +0000 (+0000) Subject: Remove definitions of double word shift plus 32 instructions. Assembler or X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ee973147ac0aad6471f5506c3278654baec4d1c0;p=oota-llvm.git Remove definitions of double word shift plus 32 instructions. Assembler or direct-object emitter should emit the appropriate shift instruction depending on the shift amount. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 76411c6d9c0..b3fbbae8605 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -28,10 +28,8 @@ def Subtract32 : SDNodeXFormgetZExtValue() - 32); }]>; -// imm32_63 predicate - True if imm is in range [32, 63]. -def imm32_63 : ImmLeaf= 32 && (int32_t)Imm < 64;}], - Subtract32>; +// shamt must fit in 6 bits. +def immZExt6 : ImmLeaf; // Is a 32-bit int. def immSExt32 : ImmLeaf(Imm);}]>; @@ -53,12 +51,7 @@ def HIGHEST : SDNodeXForm func, bits<5> isRotate, string instr_asm, SDNode OpNode>: - shift_rotate_imm; - -class shift_rotate_imm64_32 func, bits<5> isRotate, string instr_asm, - SDNode OpNode>: - shift_rotate_imm; // Jump and Link (Call) @@ -141,9 +134,6 @@ def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>; def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>; def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>; -def DSLL32 : shift_rotate_imm64_32<0x3c, 0x00, "dsll32", shl>; -def DSRL32 : shift_rotate_imm64_32<0x3e, 0x00, "dsrl32", srl>; -def DSRA32 : shift_rotate_imm64_32<0x3f, 0x00, "dsra32", sra>; def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>; def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>; def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>; @@ -151,7 +141,6 @@ def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>; // Rotate Instructions let Predicates = [HasMips64r2] in { def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>; - def DROTR32 : shift_rotate_imm64_32<0x3e, 0x01, "drotr32", rotr>; def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>; } @@ -222,7 +211,7 @@ def DEXT : ExtBase<3, "dext", CPU64Regs>; def DINS : InsBase<7, "dins", CPU64Regs>; def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), - "dsll32\t$rd, $rt, 0", [], IIAlu>; + "dsll\t$rd, $rt, 32", [], IIAlu>; def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), "sll\t$rd, $rt, 0", [], IIAlu>; @@ -249,13 +238,12 @@ def : Pat<(i64 imm:$imm), // extended loads let Predicates = [NotN64] in { - def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64 addr:$a), 0), 0)>; - def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>; + def : Pat<(extloadi32_a addr:$a), (DSRL (DSLL (LW64 addr:$a), 32), 32)>; + def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>; } let Predicates = [IsN64] in { - def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64_P8 addr:$a), 0), 0)>; - def : Pat<(zextloadi32_u addr:$a), - (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>; + def : Pat<(extloadi32_a addr:$a), (DSRL (DSLL (LW64_P8 addr:$a), 32), 32)>; + def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>; } // hi/lo relocs @@ -308,4 +296,4 @@ def : Pat<(i32 (trunc CPU64Regs:$src)), // 32-to-64-bit extension def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; -def : Pat<(i64 (zext CPURegs:$src)), (DSRL32 (DSLL64_32 CPURegs:$src), 0)>; +def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; diff --git a/test/CodeGen/Mips/mips64ext.ll b/test/CodeGen/Mips/mips64ext.ll index 33af0d852da..ae6078b829c 100644 --- a/test/CodeGen/Mips/mips64ext.ll +++ b/test/CodeGen/Mips/mips64ext.ll @@ -3,8 +3,8 @@ define i64 @zext64_32(i32 %a) nounwind readnone { entry: ; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2 -; CHECK: dsll32 $[[R1:[0-9]+]], $[[R0]], 0 -; CHECK: dsrl32 ${{[0-9]+}}, $[[R1]], 0 +; CHECK: dsll $[[R1:[0-9]+]], $[[R0]], 32 +; CHECK: dsrl ${{[0-9]+}}, $[[R1]], 32 %add = add i32 %a, 2 %conv = zext i32 %add to i64 ret i64 %conv diff --git a/test/CodeGen/Mips/mips64shift.ll b/test/CodeGen/Mips/mips64shift.ll index cc5e5085614..45d1c953227 100644 --- a/test/CodeGen/Mips/mips64shift.ll +++ b/test/CodeGen/Mips/mips64shift.ll @@ -44,21 +44,21 @@ entry: define i64 @f6(i64 %a0) nounwind readnone { entry: -; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8 +; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40 %shl = shl i64 %a0, 40 ret i64 %shl } define i64 @f7(i64 %a0) nounwind readnone { entry: -; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8 +; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = ashr i64 %a0, 40 ret i64 %shr } define i64 @f8(i64 %a0) nounwind readnone { entry: -; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8 +; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = lshr i64 %a0, 40 ret i64 %shr } @@ -94,7 +94,7 @@ entry: define i64 @f12(i64 %a0) nounwind readnone { entry: -; CHECK: drotr32 ${{[0-9]+}}, ${{[0-9]+}}, 22 +; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54 %shl = shl i64 %a0, 10 %shr = lshr i64 %a0, 54 %or = or i64 %shl, %shr