From: Chris Lattner Date: Tue, 14 Sep 2010 23:34:29 +0000 (+0000) Subject: add a terrible hack to allow out with dx is parens, a gas bug. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ef63c9a9b6f79fef91dc144db9d5f217d2b83a95;p=oota-llvm.git add a terrible hack to allow out with dx is parens, a gas bug. This fixes PR8114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113894 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 6a664ad4ce1..dae7d1298eb 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -857,6 +857,20 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, std::swap(Operands[1], Operands[2]); } + // FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx". + if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") && + Operands.size() == 3) { + X86Operand &Op = *(X86Operand*)Operands.back(); + if (Op.isMem() && Op.Mem.SegReg == 0 && + isa(Op.Mem.Disp) && + cast(Op.Mem.Disp)->getValue() == 0 && + Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) { + SMLoc Loc = Op.getEndLoc(); + Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); + delete &Op; + } + } + // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as // "f{mul*,add*,sub*,div*} $op" if ((Name.startswith("fmul") || Name.startswith("fadd") || diff --git a/test/MC/AsmParser/X86/x86_instructions.s b/test/MC/AsmParser/X86/x86_instructions.s index b895de35cce..d4444f89523 100644 --- a/test/MC/AsmParser/X86/x86_instructions.s +++ b/test/MC/AsmParser/X86/x86_instructions.s @@ -200,3 +200,13 @@ inw %dx outb $0x7f outw %dx inl %dx + + +// PR8114 +// CHECK: outb %al, %dx +// CHECK: outw %ax, %dx +// CHECK: outl %eax, %dx + +out %al, (%dx) +out %ax, (%dx) +outl %eax, (%dx)