From: Huang, Tao <huangtao@rock-chips.com>
Date: Fri, 13 May 2016 04:20:56 +0000 (+0800)
Subject: Merge branch 'linux-linaro-lsk-v4.4-android' of git://git.linaro.org/kernel/linux... 
X-Git-Tag: firefly_0821_release~2650
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f0161aad472599f8bb80ca8758fe30a60e627f56;p=firefly-linux-kernel-4.4.55.git

Merge branch 'linux-linaro-lsk-v4.4-android' of git://git.linaro.org/kernel/linux-linaro-stable.git

* linux-linaro-lsk-v4.4-android: (797 commits)
  parisc: Use generic extable search and sort routines
  arm64: kasan: Use actual memory node when populating the kernel image shadow
  arm64: mm: treat memstart_addr as a signed quantity
  arm64: lse: deal with clobbered IP registers after branch via PLT
  arm64: mm: check at build time that PAGE_OFFSET divides the VA space evenly
  arm64: kasan: Fix zero shadow mapping overriding kernel image shadow
  arm64: consistently use p?d_set_huge
  arm64: fix KASLR boot-time I-cache maintenance
  arm64: hugetlb: partial revert of 66b3923a1a0f
  arm64: make irq_stack_ptr more robust
  arm64: efi: invoke EFI_RNG_PROTOCOL to supply KASLR randomness
  efi: stub: use high allocation for converted command line
  efi: stub: add implementation of efi_random_alloc()
  efi: stub: implement efi_get_random_bytes() based on EFI_RNG_PROTOCOL
  arm64: kaslr: randomize the linear region
  arm64: add support for kernel ASLR
  arm64: add support for building vmlinux as a relocatable PIE binary
  arm64: switch to relative exception tables
  extable: add support for relative extables to search and sort routines
  scripts/sortextable: add support for ET_DYN binaries
  ...

Conflicts:
	arch/arm64/mm/dma-mapping.c
	drivers/clk/rockchip/clk-rk3368.c
	drivers/mmc/core/core.c
	drivers/mmc/core/sdio.c
	include/linux/dcache.h

Change-Id: Ibaa1e90ac735db8d9f5e542c266ef27b91616ef4
---

f0161aad472599f8bb80ca8758fe30a60e627f56
diff --cc drivers/clk/rockchip/clk-rk3188.c
index 0f78d7353d17,fe728f8dcbe4..2643a85b38fe
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@@ -754,11 -718,11 +754,12 @@@ static const char *const rk3188_critica
  	"hclk_peri",
  	"pclk_cpu",
  	"pclk_peri",
+ 	"hclk_cpubus"
  };
  
 -static void __init rk3188_common_clk_init(struct device_node *np)
 +static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
  {
 +	struct rockchip_clk_provider *ctx;
  	void __iomem *reg_base;
  	struct clk *clk;
  
diff --cc drivers/clk/rockchip/clk.c
index c5fd146c8cf2,9b6c8188efac..277f9270bf72
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@@ -105,58 -102,14 +105,63 @@@ static struct clk *rockchip_clk_registe
  				     flags);
  
  	return clk;
+ err_div:
+ 	kfree(gate);
+ err_gate:
+ 	kfree(mux);
+ 	return ERR_PTR(-ENOMEM);
  }
  
 -static struct clk *rockchip_clk_register_frac_branch(const char *name,
 +struct rockchip_clk_frac {
 +	struct notifier_block			clk_nb;
 +	struct clk_fractional_divider		div;
 +	struct clk_gate				gate;
 +
 +	struct clk_mux				mux;
 +	const struct clk_ops			*mux_ops;
 +	int					mux_frac_idx;
 +
 +	bool					rate_change_remuxed;
 +	int					rate_change_idx;
 +};
 +
 +#define to_rockchip_clk_frac_nb(nb) \
 +			container_of(nb, struct rockchip_clk_frac, clk_nb)
 +
 +static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 +					 unsigned long event, void *data)
 +{
 +	struct clk_notifier_data *ndata = data;
 +	struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
 +	struct clk_mux *frac_mux = &frac->mux;
 +	int ret = 0;
 +
 +	pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
 +		 __func__, event, ndata->old_rate, ndata->new_rate);
 +	if (event == PRE_RATE_CHANGE) {
 +		frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw);
 +		if (frac->rate_change_idx != frac->mux_frac_idx) {
 +			frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx);
 +			frac->rate_change_remuxed = 1;
 +		}
 +	} else if (event == POST_RATE_CHANGE) {
 +		/*
 +		 * The POST_RATE_CHANGE notifier runs directly after the
 +		 * divider clock is set in clk_change_rate, so we'll have
 +		 * remuxed back to the original parent before clk_change_rate
 +		 * reaches the mux itself.
 +		 */
 +		if (frac->rate_change_remuxed) {
 +			frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx);
 +			frac->rate_change_remuxed = 0;
 +		}
 +	}
 +
 +	return notifier_from_errno(ret);
 +}
 +
 +static struct clk *rockchip_clk_register_frac_branch(
 +		struct rockchip_clk_provider *ctx, const char *name,
  		const char *const *parent_names, u8 num_parents,
  		void __iomem *base, int muxdiv_offset, u8 div_flags,
  		int gate_offset, u8 gate_shift, u8 gate_flags,
diff --cc drivers/soc/rockchip/pm_domains.c
index 94a80e631ff8,4a65c5bda146..bd1f1c4e5f80
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@@ -596,16 -419,9 +596,17 @@@ static int rockchip_pm_domain_probe(str
  		if (error) {
  			dev_err(dev, "failed to handle node %s: %d\n",
  				node->name, error);
+ 			of_node_put(node);
  			goto err_out;
  		}
 +
 +		error = rockchip_pm_add_subdomain(pmu, node);
 +		if (error < 0) {
 +			dev_err(dev, "failed to handle subdomain node %s: %d\n",
 +				node->name, error);
 +			of_node_put(node);
 +			goto err_out;
 +		}
  	}
  
  	if (error) {