From: Matthias Braun <matze@braunis.de>
Date: Wed, 26 Aug 2015 20:46:49 +0000 (+0000)
Subject: FastISel: Avoid adding a successor block twice for degenerate IR.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f042f1cd8d78a8b25bddf06657441092554e08db;p=oota-llvm.git

FastISel: Avoid adding a successor block twice for degenerate IR.

This fixes http://llvm.org/PR24581

Differential Revision: http://reviews.llvm.org/D12350

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246074 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index d5011d2d62d..13b097cfc60 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1415,7 +1415,11 @@ void FastISel::finishCondBranch(const BasicBlock *BranchBB,
   if (FuncInfo.BPI)
     BranchWeight = FuncInfo.BPI->getEdgeWeight(BranchBB,
                                                TrueMBB->getBasicBlock());
-  FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
+  // Add TrueMBB as successor unless it is equal to the FalseMBB: This can
+  // happen in degenerate IR and MachineIR forbids to have a block twice in the
+  // successor/predecessor lists.
+  if (TrueMBB != FalseMBB)
+    FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
 
   fastEmitBranch(FalseMBB, DbgLoc);
 }
diff --git a/test/CodeGen/X86/fast-isel-cmp-branch.ll b/test/CodeGen/X86/fast-isel-cmp-branch.ll
index d7b64ed3a5b..e262448468e 100644
--- a/test/CodeGen/X86/fast-isel-cmp-branch.ll
+++ b/test/CodeGen/X86/fast-isel-cmp-branch.ll
@@ -1,5 +1,18 @@
-; RUN: llc -O0 -mtriple=x86_64-linux -asm-verbose=false < %s | FileCheck %s
-; RUN: llc -O0 -mtriple=x86_64-windows-itanium -asm-verbose=false < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=x86_64-linux -asm-verbose=false -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=x86_64-windows-itanium -asm-verbose=false -verify-machineinstrs < %s | FileCheck %s
+
+; Fast-isel mustn't add a block to the MBB successor/predecessor list twice.
+; The machine verifier will catch and complain about this case.
+; CHECK-LABEL: baz
+; CHECK: retq
+define void @baz() {
+entry:
+  br i1 undef, label %exit, label %exit
+
+exit:
+  ret void
+}
+
 ; rdar://8337108
 
 ; Fast-isel shouldn't try to look through the compare because it's in a