From: Xing Zheng Date: Thu, 7 Jan 2016 12:17:35 +0000 (+0800) Subject: UPSTREAM: clk: rockchip: rk3036: fix the div offset for emac clock X-Git-Tag: firefly_0821_release~2578 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f28371b4ff53e54290d35dc96a5cea13516be857;p=firefly-linux-kernel-4.4.55.git UPSTREAM: clk: rockchip: rk3036: fix the div offset for emac clock Due to reference to old version TRM, there are incorrect emac clock node. The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the child div. Change-Id: Iac08a99fc8c5420e31e68520f24875b179e3665a Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner Signed-off-by: Caesar Wang (cherry picked from git.kernel.org next/linux-next.git master commit c40519350e1d7db03e35e57509352c55948648ba) --- diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 52e9c7ea7f44..72126b74c16a 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -347,12 +347,12 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKGATE_CON(10), 5, GFLAGS), COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS), + RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0, - RK2928_CLKSEL_CON(21), 9, 5, DFLAGS, + RK2928_CLKSEL_CON(21), 4, 5, DFLAGS, RK2928_CLKGATE_CON(2), 6, GFLAGS), MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,