From: Adam Nemet Date: Tue, 24 Jun 2014 01:42:32 +0000 (+0000) Subject: [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f36c3de849d4dacbdfd79c4f4178163e09b65efa;p=oota-llvm.git [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and NDS register fields. This was simply not used in the decoder until now. Fixes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211565 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp index 804606d917b..55587d462ff 100644 --- a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp +++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp @@ -1620,7 +1620,8 @@ static int readVVVV(struct InternalInstruction* insn) { int vvvv; if (insn->vectorExtensionType == TYPE_EVEX) - vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]); + vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | + vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2])); else if (insn->vectorExtensionType == TYPE_VEX_3B) vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); else if (insn->vectorExtensionType == TYPE_VEX_2B) diff --git a/test/MC/Disassembler/X86/avx-512.txt b/test/MC/Disassembler/X86/avx-512.txt index e5ad2a9e441..b1a8aaf0d6d 100644 --- a/test/MC/Disassembler/X86/avx-512.txt +++ b/test/MC/Disassembler/X86/avx-512.txt @@ -39,6 +39,12 @@ # CHECK: vgatherdpd (%rsi,%ymm0,4), %zmm1 {%k2} 0x62 0xf2 0xfd 0x4a 0x92 0x0c 0x86 +# CHECK: vpslld $16, %zmm21, %zmm22 +0x62 0xb1 0x4d 0x40 0x72 0xf5 0x10 + +# CHECK: vpord %zmm22, %zmm21, %zmm23 +0x62 0xa1 0x55 0x40 0xeb 0xfe + ##################################################### # MASK INSTRUCTIONS # #####################################################