From: Elena Demikhovsky <elena.demikhovsky@intel.com>
Date: Sun, 4 Aug 2013 10:46:07 +0000 (+0000)
Subject: AVX-512 set: added VEXTRACTPS instruction
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f3e3417e652420a2880fe1efa98ff11936f082e1;p=oota-llvm.git

AVX-512 set: added VEXTRACTPS instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td
index 71a5d1d79b2..db90341e3c9 100644
--- a/lib/Target/X86/X86InstrAVX512.td
+++ b/lib/Target/X86/X86InstrAVX512.td
@@ -192,19 +192,16 @@ def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
 // vinsertps - insert f32 to XMM
 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
       (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
-      !strconcat("vinsertps{z}",
-                 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+      "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
       [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
       EVEX_4V;
 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
       (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
-      !strconcat("vinsertps{z}",
-                 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+      "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
       [(set VR128X:$dst, (X86insrtps VR128X:$src1,
                           (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
                           imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
 
-
 //===----------------------------------------------------------------------===//
 // AVX-512 VECTOR EXTRACT
 //---
@@ -337,3 +334,15 @@ def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
           (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
 
+// vextractps - extract 32 bits from XMM
+def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
+      (ins VR128X:$src1, u32u8imm:$src2),
+      "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+      [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
+      EVEX;
+
+def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
+      (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
+      "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+      [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
+                          addr:$dst)]>, EVEX;
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index dc1c3ea7d00..9911b8dfec0 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -6139,7 +6139,7 @@ multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
 }
 
 let ExeDomain = SSEPackedSingle in {
-  let Predicates = [HasAVX] in {
+  let Predicates = [UseAVX] in {
     defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
     def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
                     (ins VR128:$src1, i32i8imm:$src2),
diff --git a/test/CodeGen/X86/avx512-insert-extract.ll b/test/CodeGen/X86/avx512-insert-extract.ll
index 375ef5cbf34..189bdd76c98 100644
--- a/test/CodeGen/X86/avx512-insert-extract.ll
+++ b/test/CodeGen/X86/avx512-insert-extract.ll
@@ -41,4 +41,23 @@ define <8 x i64> @test4(<8 x i64> %x) nounwind {
   %eee = extractelement <8 x i64> %x, i32 4
   %rrr2 = insertelement <8 x i64> %x, i64 %eee, i32 1
   ret <8 x i64> %rrr2
-}
\ No newline at end of file
+}
+
+;CHECK: test5
+;CHECK: vextractpsz
+;CHECK: ret
+define i32 @test5(<4 x float> %x) nounwind {
+  %ef = extractelement <4 x float> %x, i32 3
+  %ei = bitcast float %ef to i32
+  ret i32 %ei
+}
+
+;CHECK: test6
+;CHECK: vextractpsz {{.*}}, (%rdi)
+;CHECK: ret
+define void @test6(<4 x float> %x, float* %out) nounwind {
+  %ef = extractelement <4 x float> %x, i32 3
+  store float %ef, float* %out, align 4
+  ret void
+}
+