From: 黄涛 Date: Wed, 22 Jan 2014 08:13:20 +0000 (+0800) Subject: ARM: rockchip: add rk3288 fpga support X-Git-Tag: firefly_0821_release~6365 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f537d4dada5423d947afa90c7f606d9c404b2e13;p=firefly-linux-kernel-4.4.55.git ARM: rockchip: add rk3288 fpga support --- diff --git a/arch/arm/boot/dts/rk3288-fpga.dts b/arch/arm/boot/dts/rk3288-fpga.dts new file mode 100644 index 000000000000..ca4a3b89fa46 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-fpga.dts @@ -0,0 +1,20 @@ +/dts-v1/; + +#include "rk3288.dtsi" + +/ { + compatible = "rockchip,rk3288-fpga"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "androidboot.console=ttyFIQ0 initrd=0x02000000,0x00800000"; + }; + + fiq-debugger { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi new file mode 100644 index 000000000000..bd9d6558459a --- /dev/null +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -0,0 +1,88 @@ +#include +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3288"; + interrupt-parent = <&gic>; + + aliases { + serial2 = &uart_dbg; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x500>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x501>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x502>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x503>; + }; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0xffc01000 0x1000>, + <0xffc02000 0x1000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + timer@ff810000 { + compatible = "rockchip,timer"; + reg = <0xff810000 0x20>; + interrupts = ; + rockchip,broadcast = <1>; + }; + + timer@ff810020 { + compatible = "rockchip,timer"; + reg = <0xff810020 0x20>; + interrupts = ; + rockchip,clocksource = <1>; + rockchip,count-up = <1>; + }; + + uart_dbg: serial@ff690000 { + compatible = "rockchip,serial"; + reg = <0xff690000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,signal-irq = <106>; + rockchip,wake-irq = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S index 72f8a2675580..ea312fa8a5a4 100644 --- a/arch/arm/include/debug/rockchip.S +++ b/arch/arm/include/debug/rockchip.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 ROCKCHIP, Inc. + * Copyright (C) 2013-2014 ROCKCHIP, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -12,11 +12,20 @@ * */ +#include <../mach-rockchip/iomap.h> #define UART_SHIFT 2 .macro addruart, rp, rv, tmp - ldr \rp, = 0x20064000 - ldr \rv, = 0xfed64000 + mrc p15, 0, \tmp, c0, c0, 0 + ldr \rv, = 0x413fc090 + cmp \tmp, \rv + ldreq \rp, = RK3188_UART2_PHYS + ldrne \rp, = RK3288_UART_DBG_PHYS + ldr \rv, = 0xff000000 + mov \tmp, \rp + bic \tmp, \tmp, #0xff000000 + bic \tmp, \tmp, #0x00f00000 + add \rv, \rv, \tmp .endm #include "8250_32.S" diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d01134d0e65f..10ac34ae4419 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -8,14 +8,12 @@ config ARCH_ROCKCHIP select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_ARCH_TIMER select HAVE_SMP select LOCAL_TIMERS if SMP select COMMON_CLK select GENERIC_CLOCKEVENTS select CLKSRC_OF if OF - help - Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs - containing the RK2928, RK30xx and RK31xx series. if ARCH_ROCKCHIP @@ -25,4 +23,7 @@ config RK_DEBUG_UART help Select a UART for debugging. -1 disable. +config RK_FPGA + bool "FPGA Board" + endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index edb2865ff494..eaa07ec49817 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -1,6 +1,7 @@ obj-y += common.o obj-y += cpu.o obj-y += rk3188.o +obj-$(CONFIG_RK_FPGA) += fpga.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_FIQ_DEBUGGER) += rk_fiq_debugger.o diff --git a/arch/arm/mach-rockchip/cpu.h b/arch/arm/mach-rockchip/cpu.h index b9820044846e..40f424207cc3 100644 --- a/arch/arm/mach-rockchip/cpu.h +++ b/arch/arm/mach-rockchip/cpu.h @@ -12,6 +12,7 @@ static inline bool cpu_is_rockchip(void) { return rockchip_soc_id; } #define ROCKCHIP_CPU_RK3066B 0x31680000 #define ROCKCHIP_CPU_RK3188 0x31880000 #define ROCKCHIP_CPU_RK319X 0x31900000 +#define ROCKCHIP_CPU_RK3288 0x32880000 static inline bool cpu_is_rk2928(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK2928; } static inline bool cpu_is_rk3026(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3026; } @@ -19,6 +20,7 @@ static inline bool cpu_is_rk30xx(void) { return (rockchip_soc_id & ROCKCHIP_CPU static inline bool cpu_is_rk3066b(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3066B; } static inline bool cpu_is_rk3188(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3188; } static inline bool cpu_is_rk319x(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK319X; } +static inline bool cpu_is_rk3288(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3288; } #define ROCKCHIP_SOC_RK2926 (ROCKCHIP_CPU_RK2928 | 0x00) #define ROCKCHIP_SOC_RK2928G (ROCKCHIP_CPU_RK2928 | 0x01) @@ -34,6 +36,7 @@ static inline bool cpu_is_rk319x(void) { return (rockchip_soc_id & ROCKCHIP_CPU #define ROCKCHIP_SOC_RK3188 (ROCKCHIP_CPU_RK3188 | 0x00) #define ROCKCHIP_SOC_RK3188PLUS (ROCKCHIP_CPU_RK3188 | 0x10) #define ROCKCHIP_SOC_RK3190 (ROCKCHIP_CPU_RK319X | 0x00) +#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00) static inline bool soc_is_rk2926(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2926; } static inline bool soc_is_rk2928g(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2928G; } @@ -49,5 +52,6 @@ static inline bool soc_is_rk3028(void) { return rockchip_soc_id == ROCKCHIP_SOC static inline bool soc_is_rk3188(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188; } static inline bool soc_is_rk3188plus(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188PLUS; } static inline bool soc_is_rk3190(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3190; } +static inline bool soc_is_rk3288(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3288; } #endif diff --git a/arch/arm/mach-rockchip/fpga.c b/arch/arm/mach-rockchip/fpga.c new file mode 100644 index 000000000000..171fd052b93a --- /dev/null +++ b/arch/arm/mach-rockchip/fpga.c @@ -0,0 +1,60 @@ +/* + * Device Tree support for Rockchip FPGA + * + * Copyright (C) 2014 ROCKCHIP, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "cpu.h" +#include "iomap.h" + +static struct map_desc rk3288_io_desc[] __initdata = { + { + .virtual = (unsigned long) RK_DEBUG_UART_VIRT, + .pfn = __phys_to_pfn(RK3288_UART_DBG_PHYS), + .length = RK3288_UART_SIZE, + .type = MT_DEVICE, + }, +}; + +static void __init rk3288_fpga_map_io(void) +{ + iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc)); + debug_ll_io_init(); + + rockchip_soc_id = ROCKCHIP_SOC_RK3288; +} + +static void __init rk3288_fpga_init_timer(void) +{ + clocksource_of_init(); +} + +static const char * const rk3288_fpga_compat[] __initconst = { + "rockchip,rk3288-fpga", + NULL, +}; + +DT_MACHINE_START(RK3288_FPGA_DT, "Rockchip RK3288 FPGA (Flattened Device Tree)") + .map_io = rk3288_fpga_map_io, + .init_time = rk3288_fpga_init_timer, + .dt_compat = rk3288_fpga_compat, +MACHINE_END diff --git a/arch/arm/mach-rockchip/iomap.h b/arch/arm/mach-rockchip/iomap.h index d7fe5f1f4dbf..d515f5f2dd77 100644 --- a/arch/arm/mach-rockchip/iomap.h +++ b/arch/arm/mach-rockchip/iomap.h @@ -1,7 +1,9 @@ #ifndef __MACH_ROCKCHIP_IOMAP_H #define __MACH_ROCKCHIP_IOMAP_H +#ifndef __ASSEMBLY__ #include +#endif #define RK_IO_ADDRESS(x) IOMEM(0xFED00000 + x) @@ -46,4 +48,11 @@ #define RK3188_UART3_PHYS 0x20068000 #define RK3188_UART_SIZE SZ_4K +#define RK3288_UART_BT_PHYS 0xff180000 +#define RK3288_UART_BB_PHYS 0xff190000 +#define RK3288_UART_DBG_PHYS 0xff690000 +#define RK3288_UART_GPS_PHYS 0xff1b0000 +#define RK3288_UART_EXP_PHYS 0xff1c0000 +#define RK3288_UART_SIZE SZ_4K + #endif