From: Ville Syrjälä Date: Thu, 23 Jan 2014 14:49:17 +0000 (+0200) Subject: drm/i915: Fix FBC_FENCE_OFF X-Git-Tag: firefly_0821_release~176^2~4105^2~62^2~70 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f64f17265977efb54e330aae1e72637d75308244;p=firefly-linux-kernel-4.4.55.git drm/i915: Fix FBC_FENCE_OFF Having a 4 byte register at 0x321b seems unlikely as that's not 4 byte aligned. Since later platforms have more or less the same FBC registers with new names, assume that FBC_FENCE_OFF is at 0x3218 just like DPFC_FENCE_YOFF. This feels like a simple typo in BSpec. 321Bh looks a lot like 3218h after all. Should still be tested on real hardware of course. But I don't have any mobile gen4 systems. Signed-off-by: Ville Syrjälä Acked-by: Chris Wilson Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ba0799518e17..8a82c018d874 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1048,7 +1048,7 @@ #define FBC_CTL_IDLE_DEBUG (3<<2) #define FBC_CTL_CPU_FENCE (1<<1) #define FBC_CTL_PLANE(plane) ((plane)<<0) -#define FBC_FENCE_OFF 0x0321b +#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ #define FBC_TAG 0x03300 #define FBC_LL_SIZE (1536)