From: Wu Liang feng Date: Mon, 8 Jun 2015 14:23:26 +0000 (+0800) Subject: usb: ehci: rename hsic and HSIC to ehci1 and EHCI1 X-Git-Tag: firefly_0821_release~4060 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f66e5a7f7017417a519ed41e4ba11b1a747e0146;p=firefly-linux-kernel-4.4.55.git usb: ehci: rename hsic and HSIC to ehci1 and EHCI1 Signed-off-by: Wu Liang feng --- diff --git a/Documentation/devicetree/bindings/usb/rockchip-usb.txt b/Documentation/devicetree/bindings/usb/rockchip-usb.txt index cf8009b3c168..5d21bd827760 100644 --- a/Documentation/devicetree/bindings/usb/rockchip-usb.txt +++ b/Documentation/devicetree/bindings/usb/rockchip-usb.txt @@ -102,10 +102,10 @@ Example: }; -HSIC +EHCI1 Required properties: - - compatible : Should be "rockchip,rk3188_rk_hsic_host" or - "rockchip,rk3288_rk_hsic_host" and so on, depending upon + - compatible : Should be "rockchip,rk3188_rk_ehci_host" or + "rockchip,rk3288_rk_ehci1_host" and so on, depending upon the SoC. - reg : Physical base address of the controller and length of memory mapped region. @@ -117,16 +117,16 @@ Required properties: Example: - RK3288 - hsic: hsic@ff5c0000 { - compatible = "rockchip,rk3288_rk_hsic_host"; + usb4: usb@ff5c0000 { + compatible = "rockchip,rk3288_rk_ehci1_host"; reg = <0xff5c0000 0x40000>; interrupts = ; - clocks = <&hsicphy_480m>, <&clk_gates7 8>, - <&hsicphy_12m>, <&usbphy_480m>, + clocks = <&ehci1phy_480m>, <&clk_gates7 8>, + <&ehci1phy_12m>, <&usbphy_480m>, <&otgphy1_480m>, <&otgphy2_480m>; - clock-names = "hsicphy_480m", "hclk_hsic", - "hsicphy_12m", "usbphy_480m", - "hsic_usbphy1", "hsic_usbphy2"; + clock-names = "ehci1phy_480m", "hclk_ehci1", + "ehci1phy_12m", "usbphy_480m", + "ehci1_usbphy1", "ehci1_usbphy2"; }; ROCKCHIP USB-PHY CONTROL diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi index 5253980aa0b8..2c7f731149dc 100755 --- a/arch/arm/boot/dts/rk3188-clocks.dtsi +++ b/arch/arm/boot/dts/rk3188-clocks.dtsi @@ -479,11 +479,11 @@ /* reg[7:6]: reserved */ - clk_hsicphy12m: hsic_phy_div { + clk_ehci1phy12m: ehci1_phy_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 6>; - clocks = <&clk_hsicphy480m>; - clock-output-names = "clk_hsicphy12m"; + clocks = <&clk_ehci1phy480m>; + clock-output-names = "clk_ehci1phy12m"; rockchip,div-type = ; #clock-cells = <0>; }; @@ -1015,12 +1015,12 @@ #address-cells = <1>; #size-cells = <1>; - clk_hsicphy480m: clk_hsicphy480m_mux { + clk_ehci1phy480m: clk_ehci1phy480m_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <0 2>; clocks = <&otgphy0_480m>, <&otgphy1_480m>, <&clk_gpll>, <&clk_cpll>; - clock-output-names = "clk_hsicphy480m"; + clock-output-names = "clk_ehci1phy480m"; #clock-cells = <0>; }; @@ -1274,7 +1274,7 @@ <&dclk_lcdc1>, <&clk_cif_in>, <&xin24m>, <&xin24m>, - <&clk_hsicphy480m>, <&clk_cif0>, + <&clk_ehci1phy480m>, <&clk_cif0>, <&xin24m>, <&clk_vepu>, <&clk_vepu>, <&clk_vdpu>, @@ -1291,7 +1291,7 @@ * clk_cif as virtual */ "timer2", "timer4", - "clk_hsicphy480m", "clk_cif0", + "clk_ehci1phy480m", "clk_cif0", "timer5", "clk_vepu", "g_h_vepu", "clk_vdpu", @@ -1420,7 +1420,7 @@ "g_h_emac", "g_h_spdif", "g_h_i2s0_2ch", "g_h_otg1", - "g_h_hsic", "g_h_hsadc", + "g_h_ehci1", "g_h_hsadc", "g_h_pidf", "g_p_timer0", "reserved", "g_p_timer2", diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 28a7d6c45f39..74d67bf7a936 100755 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -767,14 +767,14 @@ clock-names = "clk_usbphy1", "hclk_usb1"; }; - hsic: hsic@10240000 { - compatible = "rockchip,rk3188_rk_hsic_host"; + usb2: usb@10240000 { + compatible = "rockchip,rk3188_rk_ehci_host"; reg = <0x10240000 0x40000>; interrupts = ; - clocks = <&clk_hsicphy480m>, <&clk_gates7 4>, - <&clk_hsicphy12m>, <&otgphy1_480m>; - clock-names = "hsicphy_480m", "hclk_hsic", - "hsicphy_12m", "hsic_usbphy1"; + clocks = <&clk_ehci1phy480m>, <&clk_gates7 4>, + <&clk_ehci1phy12m>, <&otgphy1_480m>; + clock-names = "ehci1phy_480m", "hclk_ehci1", + "ehci1phy_12m", "ehci1_usbphy1"; }; vmac@10204000 { diff --git a/arch/arm/boot/dts/rk3288-clocks.dtsi b/arch/arm/boot/dts/rk3288-clocks.dtsi index 9a1769372ac6..ce6d3395e83c 100755 --- a/arch/arm/boot/dts/rk3288-clocks.dtsi +++ b/arch/arm/boot/dts/rk3288-clocks.dtsi @@ -862,11 +862,11 @@ #clock-cells = <0>; }; - hsicphy_12m_div: hsicphy_12m_div { + ehci1phy_12m_div: ehci1phy_12m_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 6>; - clocks = <&hsicphy_480m>; - clock-output-names = "hsicphy_12m_div"; + clocks = <&ehci1phy_480m>; + clock-output-names = "ehci1phy_12m_div"; rockchip,div-type = ; #clock-cells = <0>; }; @@ -1483,19 +1483,19 @@ #address-cells = <1>; #size-cells = <1>; - hsicphy_480m: hsicphy_480m_mux { + ehci1phy_480m: ehci1phy_480m_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <0 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>; - clock-output-names = "hsicphy_480m"; + clock-output-names = "ehci1phy_480m"; #clock-cells = <0>; }; - hsicphy_12m: hsicphy_12m_mux { + ehci1phy_12m: ehci1phy_12m_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <2 1>; - clocks = <&clk_gates13 9>, <&hsicphy_12m_div>; - clock-output-names = "hsicphy_12m"; + clocks = <&clk_gates13 9>, <&ehci1phy_12m_div>; + clock-output-names = "ehci1phy_12m"; #clock-cells = <0>; }; @@ -2249,7 +2249,7 @@ <&aclk_vio1>, <&dclk_lcdc1>, <&clk_rga>, <&aclk_rga>, - <&hsicphy_480m>, <&clk_cif_pll>, + <&ehci1phy_480m>, <&clk_cif_pll>, <&dummy>, <&clk_vepu>, <&dummy>, <&clk_vdpu>, @@ -2262,7 +2262,7 @@ "aclk_vio1", "dclk_lcdc1", "clk_rga", "aclk_rga", - "hsicphy_480m", "clk_cif_pll", + "ehci1phy_480m", "clk_cif_pll", /*Not use hclk_vpu_gate tmp, fixme*/ "reserved", "clk_vepu", @@ -2398,7 +2398,7 @@ "g_hclk_otg0", "g_pmu_hclk_otg0", "g_hclk_host0", "g_hclk_host1", - "g_hclk_hsic", "g_hclk_usb_peri", + "g_hclk_ehci1", "g_hclk_usb_peri", "g_hp_ahb_arbi", "g_aclk_peri_niu", "g_h_emem_peri", "g_hclk_mem_peri", @@ -2598,7 +2598,7 @@ "clk_otgphy0", "clk_otgphy1", "clk_otgphy2", "clk_otg_adp", - "g_clk_c2c_host", "g_clk_hsic_12m", + "g_clk_c2c_host", "g_clk_ehci1_12m", "g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1", "g_clk_wifi", "aclk_hevc", diff --git a/arch/arm/boot/dts/rk3288-fpga.dts b/arch/arm/boot/dts/rk3288-fpga.dts index 5eee1dd814e5..52a05a137d2a 100755 --- a/arch/arm/boot/dts/rk3288-fpga.dts +++ b/arch/arm/boot/dts/rk3288-fpga.dts @@ -412,8 +412,8 @@ interrupts = ; }; - usb5: hsic@ff5c0000 { - compatible = "rockchip,rk3288_rk_hsic_host"; + usb5: usb@ff5c0000 { + compatible = "rockchip,rk3288_rk_ehci1_host"; reg = <0xff5c0000 0x40000>; interrupts = ; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ea3c68d6aed8..d8dd33d49ad6 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1139,19 +1139,19 @@ status = "disabled"; }; - hsic: hsic@ff5c0000 { - compatible = "rockchip,rk3288_rk_hsic_host"; + usb4: usb@ff5c0000 { + compatible = "rockchip,rk3288_rk_ehci1_host"; reg = <0xff5c0000 0x40000>; interrupts = ; - clocks = <&hsicphy_480m>, <&clk_gates7 8>, - <&hsicphy_12m>, <&usbphy_480m>, + clocks = <&ehci1phy_480m>, <&clk_gates7 8>, + <&ehci1phy_12m>, <&usbphy_480m>, <&otgphy1_480m>, <&otgphy2_480m>; - clock-names = "hsicphy_480m", "hclk_hsic", - "hsicphy_12m", "usbphy_480m", - "hsic_usbphy1", "hsic_usbphy2"; - resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>, - <&reset RK3288_SOFT_RST_HSICPHY>; - reset-names = "hsic_ahb", "hsic_aux", "hsic_phy"; + clock-names = "ehci1phy_480m", "hclk_ehci1", + "ehci1phy_12m", "usbphy_480m", + "ehci1_usbphy1", "ehci1_usbphy2"; + resets = <&reset RK3288_SOFT_RST_EHCI1>, <&reset RK3288_SOFT_RST_EHCI1_AUX>, + <&reset RK3288_SOFT_RST_EHCI1PHY>; + reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy"; }; gmac: eth@ff290000 { diff --git a/arch/arm/mach-rockchip/ddr_rk30.c b/arch/arm/mach-rockchip/ddr_rk30.c index 072b9d6aa646..000b07ec26e7 100755 --- a/arch/arm/mach-rockchip/ddr_rk30.c +++ b/arch/arm/mach-rockchip/ddr_rk30.c @@ -282,7 +282,7 @@ typedef volatile struct tagREG_FILE_RK3066B uint32 GRF_UOC2_CON[2]; uint32 reserved2; uint32 GRF_UOC3_CON[2]; - uint32 GRF_HSIC_STAT; + uint32 GRF_EHCI_STAT; uint32 GRF_OS_REG[8]; } REG_FILE_RK3066B, *pREG_FILE_RK3066B; diff --git a/arch/arm64/boot/dts/rk3368-clocks.dtsi b/arch/arm64/boot/dts/rk3368-clocks.dtsi index 4093fa6ad188..39bda43e4acc 100644 --- a/arch/arm64/boot/dts/rk3368-clocks.dtsi +++ b/arch/arm64/boot/dts/rk3368-clocks.dtsi @@ -1246,21 +1246,21 @@ /* 7:0 reserved */ - hsic_usb_480m: hsic_usb_480m_mux { + ehci1_usb_480m: ehci1_usb_480m_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 1>; clocks = <&usbotg_480m_out>, <&dummy>; - clock-output-names = "hsic_usb_480m"; + clock-output-names = "ehci1_usb_480m"; #clock-cells = <0>; }; /* 11:9 reserved */ - hsicphy_480m: hsicphy_480m_mux { + ehci1phy_480m: ehci1phy_480m_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <12 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>; - clock-output-names = "hsicphy_480m"; + clocks = <&clk_cpll>, <&clk_gpll>, <&ehci1_usb_480m>, <&ehci1_usb_480m>; + clock-output-names = "ehci1phy_480m"; #clock-cells = <0>; }; }; @@ -2285,11 +2285,11 @@ compatible = "rockchip,rk3188-gate-clk"; reg = <0x0220 0x4>; clocks = - <&hsic_usb_480m>, <&xin24m>, + <&ehci1_usb_480m>, <&xin24m>, <&dummy>, <&dummy>, <&clk_32k_mux>, <&dummy>, - <&xin12m>, <&hsicphy_480m>, + <&xin12m>, <&ehci1phy_480m>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, @@ -2298,11 +2298,11 @@ <&dummy>, <&dummy>; clock-output-names = - "hsic_usb_480m", "clk_otgphy0", + "ehci1_usb_480m", "clk_otgphy0", "reserved", "reserved", "g_clk_otg_adp", "reserved",/* bit4: clk_otg_adp */ - "hsicphy_12m", "hsicphy_480m", + "ehci1phy_12m", "ehci1phy_480m", "reserved", "reserved", "reserved", "reserved", @@ -2685,7 +2685,7 @@ "g_pclk_tsadc", "g_hclk_otg0", "g_h_pmu_otg0", "g_hclk_host0", - "reserved", "g_hclk_hsic", + "reserved", "g_hclk_ehci1", "g_h_usb_peri", "g_h_p_ahb_arbi", "g_a_peri_niu", "g_h_emem_peri", diff --git a/arch/arm64/boot/dts/rk3368.dtsi b/arch/arm64/boot/dts/rk3368.dtsi index 00f649f6f812..c6a5f4f14bb4 100644 --- a/arch/arm64/boot/dts/rk3368.dtsi +++ b/arch/arm64/boot/dts/rk3368.dtsi @@ -1439,20 +1439,20 @@ clock-names = "clk_usbphy0", "hclk_ohci"; }; - usb_hsic: usb@ff5c0000 { - compatible = "rockchip,rk3288_rk_hsic_host"; + usb_ehci1: usb@ff5c0000 { + compatible = "rockchip,rk3288_rk_ehci1_host"; reg = <0x0 0xff5c0000 0x0 0x40000>; interrupts = ; /* - clocks = <&hsicphy_480m>, <&clk_gates7 8>, - <&hsicphy_12m>, <&usbphy_480m>, + clocks = <&ehci1phy_480m>, <&clk_gates7 8>, + <&ehci1phy_12m>, <&usbphy_480m>, <&otgphy1_480m>, <&otgphy2_480m>; - clock-names = "hsicphy_480m", "hclk_hsic", - "hsicphy_12m", "usbphy_480m", - "hsic_usbphy1", "hsic_usbphy2"; - resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>, - <&reset RK3288_SOFT_RST_HSICPHY>; - reset-names = "hsic_ahb", "hsic_aux", "hsic_phy"; + clock-names = "ehci1phy_480m", "hclk_ehci1", + "ehci1phy_12m", "usbphy_480m", + "ehci1_usbphy1", "ehci1_usbphy2"; + resets = <&reset RK3368_SRST_EHCI1>, <&reset RK3368_SRST_EHCI1_AUX>, + <&reset RK3368_SRST_EHCI1PHY>; + reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy"; */ status = "disabled"; }; diff --git a/drivers/usb/dwc_otg_310/usbdev_grf_regs.h b/drivers/usb/dwc_otg_310/usbdev_grf_regs.h index 8b4a72748b6f..275820311f35 100755 --- a/drivers/usb/dwc_otg_310/usbdev_grf_regs.h +++ b/drivers/usb/dwc_otg_310/usbdev_grf_regs.h @@ -25,7 +25,7 @@ typedef volatile struct tag_grf_uoc1_reg { } GRF_UOC1_REG, *pGRF_UOC1_REG; typedef volatile struct tag_grf_uoc2_reg { - /* RK3188: HISC PHY + /* RK3188: EHCI1 PHY * RK3288: HOST1 DWC_OTG */ u32 CON0; @@ -35,8 +35,8 @@ typedef volatile struct tag_grf_uoc2_reg { } GRF_UOC2_REG, *pGRF_UOC2_REG; typedef volatile struct tag_grf_uoc3_reg { - /* RK3188: HSIC CTLR - * RK3288: HSIC PHY + /* RK3188: EHCI1 CTLR + * RK3288: EHCI1 PHY */ u32 CON0; u32 CON1; @@ -45,7 +45,7 @@ typedef volatile struct tag_grf_uoc3_reg { } GRF_UOC3_REG, *pGRF_UOC3_REG; typedef volatile struct tag_grf_uoc4_reg { - /* RK3288: HSIC CTLR */ + /* RK3288: EHCI1 CTLR */ u32 CON0; u32 CON1; u32 CON2; @@ -74,16 +74,16 @@ typedef volatile struct tag_grf_soc_status0_rk3188 { typedef volatile struct tag_grf_soc_status1_rk3288 { unsigned reserved2:16; - unsigned hsic_ehci_usbsts:6; - unsigned hsic_ehci_lpsmc_state:4; + unsigned ehci1_usbsts:6; + unsigned ehci1_lpsmc_state:4; unsigned reserved1:6; } GRF_SOC_STATUS1_RK3288, *pGRF_SOC_STATUS1_RK3288; typedef volatile struct tag_grf_soc_status2_rk3288 { - /* HSIC */ - unsigned hsic_ehci_xfer_cnt:11; - unsigned hsic_ehci_xfer_prdc:1; + /* EHCI1 */ + unsigned ehci1_xfer_cnt:11; + unsigned ehci1_xfer_prdc:1; unsigned reserved2:1; /* OTG20 */ unsigned otg_vbusvalid:1; diff --git a/drivers/usb/dwc_otg_310/usbdev_rk.h b/drivers/usb/dwc_otg_310/usbdev_rk.h index e5fef02622db..c4b0dd72f550 100755 --- a/drivers/usb/dwc_otg_310/usbdev_rk.h +++ b/drivers/usb/dwc_otg_310/usbdev_rk.h @@ -61,11 +61,11 @@ extern void rk_send_wakeup_key(void); /* rk3188 platform data */ extern struct dwc_otg_platform_data usb20otg_pdata_rk3188; extern struct dwc_otg_platform_data usb20host_pdata_rk3188; -extern struct rkehci_platform_data rkhsic_pdata_rk3188; +extern struct rkehci_platform_data rkehci_pdata_rk3188; /* rk3288 platform data */ extern struct dwc_otg_platform_data usb20otg_pdata_rk3288; extern struct dwc_otg_platform_data usb20host_pdata_rk3288; -extern struct rkehci_platform_data rkhsic_pdata_rk3288; +extern struct rkehci_platform_data rkehci1_pdata_rk3288; extern struct rkehci_platform_data rkehci_pdata_rk3288; extern struct rkehci_platform_data rkohci_pdata_rk3288; /* rk3036 platform data */ @@ -103,9 +103,9 @@ struct dwc_otg_platform_data { struct rkehci_platform_data { struct device *dev; - struct clk *hclk_hsic; - struct clk *hsic_phy_480m; - struct clk *hsic_phy_12m; + struct clk *hclk_ehci; + struct clk *ehci_phy_480m; + struct clk *ehci_phy_12m; struct clk *phyclk; struct clk *ahbclk; void (*hw_init) (void); diff --git a/drivers/usb/dwc_otg_310/usbdev_rk30.c b/drivers/usb/dwc_otg_310/usbdev_rk30.c index 6494facbf176..92c1d016bd0e 100755 --- a/drivers/usb/dwc_otg_310/usbdev_rk30.c +++ b/drivers/usb/dwc_otg_310/usbdev_rk30.c @@ -289,11 +289,11 @@ struct dwc_otg_platform_data usb20host_pdata_rk3188 = { }; #endif -#ifdef CONFIG_USB_EHCI_RKHSIC -static void rk_hsic_hw_init(void) +#ifdef CONFIG_USB_EHCI1_RK +static void rk_ehci1_hw_init(void) { /* usb phy config init - * hsic phy config init, set hsicphy_txsrtune */ + * ehci1 phy config init, set ehci1phy_txsrtune */ control_usb->grf_uoc2_base->CON0 = ((0xf << 6) << 16) | (0xf << 6); /* other haredware init @@ -309,79 +309,79 @@ static void rk_hsic_hw_init(void) control_usb->grf_uoc3_base->CON0 = 0x00ff00bc; } -static void rk_hsic_clock_init(void *pdata) +static void rk_ehci1_clock_init(void *pdata) { - /* By default, hsicphy_480m's parent is otg phy 480MHz clk + /* By default, ehci1phy_480m's parent is otg phy 480MHz clk * rk3188 must use host phy 480MHz clk, because if otg bypass * to uart mode, otg phy 480MHz clk will be closed automatically */ struct rkehci_platform_data *usbpdata = pdata; - struct clk *ahbclk, *phyclk480m_hsic, *phyclk12m_hsic, *phyclk_usbphy1; + struct clk *ahbclk, *phyclk480m_ehci1, *phyclk12m_ehci1, *phyclk_usbphy1; - phyclk480m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_480m"); - if (IS_ERR(phyclk480m_hsic)) { - dev_err(usbpdata->dev, "Failed to get hsicphy_480m\n"); + phyclk480m_ehci1 = devm_clk_get(usbpdata->dev, "ehci1phy_480m"); + if (IS_ERR(phyclk480m_ehci1)) { + dev_err(usbpdata->dev, "Failed to get ehci1phy_480m\n"); return; } - phyclk12m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_12m"); - if (IS_ERR(phyclk12m_hsic)) { - dev_err(usbpdata->dev, "Failed to get hsicphy_12m\n"); + phyclk12m_ehci1 = devm_clk_get(usbpdata->dev, "ehci1phy_12m"); + if (IS_ERR(phyclk12m_ehci1)) { + dev_err(usbpdata->dev, "Failed to get ehci1phy_12m\n"); return; } - phyclk_usbphy1 = devm_clk_get(usbpdata->dev, "hsic_usbphy1"); + phyclk_usbphy1 = devm_clk_get(usbpdata->dev, "ehci1_usbphy1"); if (IS_ERR(phyclk_usbphy1)) { - dev_err(usbpdata->dev, "Failed to get hsic_usbphy1\n"); + dev_err(usbpdata->dev, "Failed to get ehci1_usbphy1\n"); return; } - ahbclk = devm_clk_get(usbpdata->dev, "hclk_hsic"); + ahbclk = devm_clk_get(usbpdata->dev, "hclk_ehci1"); if (IS_ERR(ahbclk)) { - dev_err(usbpdata->dev, "Failed to get hclk_hsic\n"); + dev_err(usbpdata->dev, "Failed to get hclk_ehci1\n"); return; } - clk_set_parent(phyclk480m_hsic, phyclk_usbphy1); + clk_set_parent(phyclk480m_ehci1, phyclk_usbphy1); - usbpdata->hclk_hsic = ahbclk; - usbpdata->hsic_phy_480m = phyclk480m_hsic; - usbpdata->hsic_phy_12m = phyclk12m_hsic; + usbpdata->hclk_ehci = ahbclk; + usbpdata->ehci_phy_480m = phyclk480m_ehci1; + usbpdata->ehci_phy_12m = phyclk12m_ehci1; } -static void rk_hsic_clock_enable(void *pdata, int enable) +static void rk_ehci1_clock_enable(void *pdata, int enable) { struct rkehci_platform_data *usbpdata = pdata; if (enable == usbpdata->clk_status) return; if (enable) { - clk_prepare_enable(usbpdata->hclk_hsic); - clk_prepare_enable(usbpdata->hsic_phy_480m); - clk_prepare_enable(usbpdata->hsic_phy_12m); + clk_prepare_enable(usbpdata->hclk_ehci); + clk_prepare_enable(usbpdata->ehci_phy_480m); + clk_prepare_enable(usbpdata->ehci_phy_12m); usbpdata->clk_status = 1; } else { - clk_disable_unprepare(usbpdata->hclk_hsic); - clk_disable_unprepare(usbpdata->hsic_phy_480m); - clk_disable_unprepare(usbpdata->hsic_phy_12m); + clk_disable_unprepare(usbpdata->hclk_ehci); + clk_disable_unprepare(usbpdata->ehci_phy_480m); + clk_disable_unprepare(usbpdata->ehci_phy_12m); usbpdata->clk_status = 0; } } -static void rk_hsic_soft_reset(void *pdata, enum rkusb_rst_flag rst_type) +static void rk_ehci1_soft_reset(void *pdata, enum rkusb_rst_flag rst_type) { } -struct rkehci_platform_data rkhsic_pdata_rk3188 = { - .hclk_hsic = NULL, - .hsic_phy_12m = NULL, - .hsic_phy_480m = NULL, +struct rkehci_platform_data rkehci_pdata_rk3188 = { + .hclk_ehci = NULL, + .ehci_phy_12m = NULL, + .ehci_phy_480m = NULL, .clk_status = -1, - .hw_init = rk_hsic_hw_init, - .clock_init = rk_hsic_clock_init, - .clock_enable = rk_hsic_clock_enable, - .soft_reset = rk_hsic_soft_reset, + .hw_init = rk_ehci1_hw_init, + .clock_init = rk_ehci1_clock_init, + .clock_enable = rk_ehci1_clock_enable, + .soft_reset = rk_ehci1_soft_reset, }; #endif diff --git a/drivers/usb/dwc_otg_310/usbdev_rk3190_grf_regs.h b/drivers/usb/dwc_otg_310/usbdev_rk3190_grf_regs.h index ee14bb1b22e6..5100dbc2e66b 100755 --- a/drivers/usb/dwc_otg_310/usbdev_rk3190_grf_regs.h +++ b/drivers/usb/dwc_otg_310/usbdev_rk3190_grf_regs.h @@ -23,12 +23,12 @@ typedef volatile struct tag_grf_uoc1_reg { u32 CON1; } GRF_UOC1_REG, *pGRF_UOC1_REG; -typedef volatile struct tag_grf_hsic_reg { +typedef volatile struct tag_grf_ehci_reg { u32 PHY_CON0; u32 PHY_CON1; u32 CTRLER_CON0; u32 CTRLER_CON1; -} GRF_HSIC_REG, *pGRF_HSIC_REG; +} GRF_EHCI_REG, *pGRF_EHCI_REG; typedef volatile struct tag_grf_usbphy_reg { u32 CON0; diff --git a/drivers/usb/dwc_otg_310/usbdev_rk32.c b/drivers/usb/dwc_otg_310/usbdev_rk32.c index dd0d051b7bce..288b962ff4c6 100755 --- a/drivers/usb/dwc_otg_310/usbdev_rk32.c +++ b/drivers/usb/dwc_otg_310/usbdev_rk32.c @@ -206,7 +206,7 @@ static void usb20host_hw_init(void) { /* usb phy config init * set common_on = 0, in suspend mode, host1 PLL blocks remain powered. - * for RK3288, hsic and other modules use host1 (DWC_OTG) 480M phy clk. + * for RK3288, ehci1 and other modules use host1 (DWC_OTG) 480M phy clk. */ control_usb->grf_uoc2_base->CON0 = (1 << 16) | 0; @@ -362,11 +362,11 @@ struct dwc_otg_platform_data usb20host_pdata_rk3288 = { #endif -#ifdef CONFIG_USB_EHCI_RKHSIC -static void rk_hsic_hw_init(void) +#ifdef CONFIG_USB_EHCI1_RK +static void rk_ehci1_hw_init(void) { /* usb phy config init - * hsic phy config init, set hsicphy_txsrtune */ + * ehci1 phy config init, set ehci1phy_txsrtune */ control_usb->grf_uoc3_base->CON0 = ((0xf << 6) << 16) | (0xf << 6); /* other haredware init @@ -382,91 +382,91 @@ static void rk_hsic_hw_init(void) control_usb->grf_uoc4_base->CON0 = 0x00ff00bc; } -static void rk_hsic_clock_init(void *pdata) +static void rk_ehci1_clock_init(void *pdata) { - /* By default, hsicphy_480m's parent is otg phy 480MHz clk + /* By default, ehci1phy_480m's parent is otg phy 480MHz clk * rk3188 must use host phy 480MHz clk, because if otg bypass * to uart mode, otg phy 480MHz clk will be closed automatically */ struct rkehci_platform_data *usbpdata = pdata; - struct clk *ahbclk, *phyclk480m_hsic, *phyclk12m_hsic; + struct clk *ahbclk, *phyclk480m_ehci1, *phyclk12m_ehci1; - phyclk480m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_480m"); - if (IS_ERR(phyclk480m_hsic)) { - dev_err(usbpdata->dev, "Failed to get hsicphy_480m\n"); + phyclk480m_ehci1 = devm_clk_get(usbpdata->dev, "ehci1phy_480m"); + if (IS_ERR(phyclk480m_ehci1)) { + dev_err(usbpdata->dev, "Failed to get ehci1phy_480m\n"); return; } - phyclk12m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_12m"); - if (IS_ERR(phyclk12m_hsic)) { - dev_err(usbpdata->dev, "Failed to get hsicphy_12m\n"); + phyclk12m_ehci1 = devm_clk_get(usbpdata->dev, "ehci1phy_12m"); + if (IS_ERR(phyclk12m_ehci1)) { + dev_err(usbpdata->dev, "Failed to get ehci1phy_12m\n"); return; } - ahbclk = devm_clk_get(usbpdata->dev, "hclk_hsic"); + ahbclk = devm_clk_get(usbpdata->dev, "hclk_ehci1"); if (IS_ERR(ahbclk)) { - dev_err(usbpdata->dev, "Failed to get hclk_hsic\n"); + dev_err(usbpdata->dev, "Failed to get hclk_ehci1\n"); return; } - usbpdata->hclk_hsic = ahbclk; - usbpdata->hsic_phy_480m = phyclk480m_hsic; - usbpdata->hsic_phy_12m = phyclk12m_hsic; + usbpdata->hclk_ehci = ahbclk; + usbpdata->ehci_phy_480m = phyclk480m_ehci1; + usbpdata->ehci_phy_12m = phyclk12m_ehci1; } -static void rk_hsic_clock_enable(void *pdata, int enable) +static void rk_ehci1_clock_enable(void *pdata, int enable) { struct rkehci_platform_data *usbpdata = pdata; if (enable == usbpdata->clk_status) return; if (enable) { - clk_prepare_enable(usbpdata->hclk_hsic); - clk_prepare_enable(usbpdata->hsic_phy_480m); - clk_prepare_enable(usbpdata->hsic_phy_12m); + clk_prepare_enable(usbpdata->hclk_ehci); + clk_prepare_enable(usbpdata->ehci_phy_480m); + clk_prepare_enable(usbpdata->ehci_phy_12m); usbpdata->clk_status = 1; } else { - clk_disable_unprepare(usbpdata->hclk_hsic); - clk_disable_unprepare(usbpdata->hsic_phy_480m); - clk_disable_unprepare(usbpdata->hsic_phy_12m); + clk_disable_unprepare(usbpdata->hclk_ehci); + clk_disable_unprepare(usbpdata->ehci_phy_480m); + clk_disable_unprepare(usbpdata->ehci_phy_12m); usbpdata->clk_status = 0; } } -static void rk_hsic_soft_reset(void *pdata, enum rkusb_rst_flag rst_type) +static void rk_ehci1_soft_reset(void *pdata, enum rkusb_rst_flag rst_type) { struct rkehci_platform_data *usbpdata = pdata; - struct reset_control *rst_hsic_h, *rst_hsic_a, *rst_hsic_p; + struct reset_control *rst_ehci1_h, *rst_ehci1_a, *rst_ehci1_p; - rst_hsic_h = devm_reset_control_get(usbpdata->dev, "hsic_ahb"); - rst_hsic_a = devm_reset_control_get(usbpdata->dev, "hsic_aux"); - rst_hsic_p = devm_reset_control_get(usbpdata->dev, "hsic_phy"); + rst_ehci1_h = devm_reset_control_get(usbpdata->dev, "ehci1_ahb"); + rst_ehci1_a = devm_reset_control_get(usbpdata->dev, "ehci1_aux"); + rst_ehci1_p = devm_reset_control_get(usbpdata->dev, "ehci1_phy"); - reset_control_assert(rst_hsic_h); - reset_control_assert(rst_hsic_a); - reset_control_assert(rst_hsic_p); + reset_control_assert(rst_ehci1_h); + reset_control_assert(rst_ehci1_a); + reset_control_assert(rst_ehci1_p); udelay(5); - reset_control_deassert(rst_hsic_h); - reset_control_deassert(rst_hsic_a); - reset_control_deassert(rst_hsic_p); + reset_control_deassert(rst_ehci1_h); + reset_control_deassert(rst_ehci1_a); + reset_control_deassert(rst_ehci1_p); mdelay(2); - /* HSIC per-port reset */ + /* EHCI1 per-port reset */ control_usb->grf_uoc3_base->CON0 = ((1 << 10) << 16) | (1 << 10); udelay(2); control_usb->grf_uoc3_base->CON0 = ((1 << 10) << 16) | (0 << 10); udelay(2); } -struct rkehci_platform_data rkhsic_pdata_rk3288 = { - .hclk_hsic = NULL, - .hsic_phy_12m = NULL, - .hsic_phy_480m = NULL, +struct rkehci_platform_data rkehci1_pdata_rk3288 = { + .hclk_ehci = NULL, + .ehci_phy_12m = NULL, + .ehci_phy_480m = NULL, .clk_status = -1, - .hw_init = rk_hsic_hw_init, - .clock_init = rk_hsic_clock_init, - .clock_enable = rk_hsic_clock_enable, - .soft_reset = rk_hsic_soft_reset, + .hw_init = rk_ehci1_hw_init, + .clock_init = rk_ehci1_clock_init, + .clock_enable = rk_ehci1_clock_enable, + .soft_reset = rk_ehci1_soft_reset, }; #endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d360a215d956..56f2a13bbc43 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -98,13 +98,13 @@ config USB_FSL_MPH_DR_OF if USB_EHCI_HCD -config USB_EHCI_RKHSIC - tristate "Rockchip EHCI HSIC support" +config USB_EHCI1_RK + tristate "Rockchip EHCI1 support" depends on ARCH_ROCKCHIP select USB_EHCI_ROOT_HUB_TT default n ---help--- - Enables support for the HSIC USB controller on the RK platform. + Enables support for the EHCI1 USB controller on the RK platform. config USB_EHCI_RK tristate "Rockchip EHCI HOST20 support" diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 32025a9a31a7..b65c8dc53ae6 100755 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1271,9 +1271,9 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_hcd_tilegx_driver #endif -#ifdef CONFIG_USB_EHCI_RKHSIC -#include "ehci-rkhsic.c" -#define ROCKCHIP_PLATFORM_DRIVER ehci_rkhsic_driver +#ifdef CONFIG_USB_EHCI1_RK +#include "ehci1-rockchip.c" +#define ROCKCHIP_PLATFORM_DRIVER ehci1_rk_driver #endif #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP diff --git a/drivers/usb/host/ehci-rkhsic.c b/drivers/usb/host/ehci-rkhsic.c deleted file mode 100755 index 1fa16bfa2a39..000000000000 --- a/drivers/usb/host/ehci-rkhsic.c +++ /dev/null @@ -1,388 +0,0 @@ -/* ehci-msm.c - HSUSB Host Controller Driver Implementation - * - * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. - * - * Partly derived from ehci-fsl.c and ehci-hcd.c - * Copyright (c) 2000-2004 by David Brownell - * Copyright (c) 2005 MontaVista Software - * - * All source code in this file is licensed under the following license except - * where indicated. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * See the GNU General Public License for more details. - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can find it at http://www.fsf.org - */ - -# include -# include -# include -# include -# include -# include -# include "ehci.h" -# include "../dwc_otg_310/usbdev_rk.h" - -static int rkhsic_status = 1; -static struct ehci_hcd *g_hsic_ehci; -#define HSIC_EHCI_PRINT(x...) printk(KERN_INFO "HSIC_EHCI: " x) - -static struct rkehci_pdata_id rkhsic_pdata[] = { - { - .name = "rk3188-hsic", - .pdata = &rkhsic_pdata_rk3188, - }, - { - .name = "rk3288-hsic", - .pdata = &rkhsic_pdata_rk3288, - }, - {}, -}; - -static void ehci_rkhsic_port_power(struct ehci_hcd *ehci, int is_on) -{ - unsigned port; - - if (!HCS_PPC(ehci->hcs_params)) - return; - - ehci_dbg(ehci, "...power%s ports...\n", is_on ? "up" : "down"); - for (port = HCS_N_PORTS(ehci->hcs_params); port > 0;) - (void)ehci_hub_control(ehci_to_hcd(ehci), - is_on ? SetPortFeature : - ClearPortFeature, USB_PORT_FEAT_POWER, - port--, NULL, 0); - /* Flush those writes */ - ehci_readl(ehci, &ehci->regs->command); - msleep(20); -} - -static struct hc_driver rk_hsic_driver = { - .description = hcd_name, - .product_desc = "Rockchip On-Chip HSIC EHCI Host Controller", - .hcd_priv_size = sizeof(struct ehci_hcd), - - /* - * generic hardware linkage - */ - .irq = ehci_irq, - .flags = HCD_USB2 | HCD_MEMORY, - - .reset = ehci_init, - .start = ehci_run, - - .stop = ehci_stop, - .shutdown = ehci_shutdown, - - /* - * managing i/o requests and associated device resources - */ - .urb_enqueue = ehci_urb_enqueue, - .urb_dequeue = ehci_urb_dequeue, - .endpoint_disable = ehci_endpoint_disable, - .endpoint_reset = ehci_endpoint_reset, - .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, - - /* - * scheduling support - */ - .get_frame_number = ehci_get_frame, - - /* - * root hub support - */ - .hub_status_data = ehci_hub_status_data, - .hub_control = ehci_hub_control, - .relinquish_port = ehci_relinquish_port, - .port_handed_over = ehci_port_handed_over, - - /* - * PM support - */ -#ifdef CONFIG_PM - .bus_suspend = ehci_bus_suspend, - .bus_resume = ehci_bus_resume, -#endif -}; - -static ssize_t ehci_rkhsic_power_show(struct device *_dev, - struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", rkhsic_status); -} - -static ssize_t ehci_rkhsic_power_store(struct device *_dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - uint32_t val = simple_strtoul(buf, NULL, 16); - struct usb_hcd *hcd = dev_get_drvdata(_dev); - struct ehci_hcd *ehci = hcd_to_ehci(hcd); - struct rkehci_platform_data *pldata = _dev->platform_data; - - printk("%s: %d setting to: %d\n", __func__, rkhsic_status, val); - if (val == rkhsic_status) - goto out; - - rkhsic_status = val; - switch (val) { - case 0: /* power down */ - ehci_rkhsic_port_power(ehci, 0); - writel_relaxed(0, hcd->regs + 0xb0); - dsb(); - msleep(5); - usb_remove_hcd(hcd); - break; - case 1: /* power on */ - pldata->soft_reset(pldata, RST_POR); - usb_add_hcd(hcd, hcd->irq, IRQF_DISABLED | IRQF_SHARED); - - ehci_rkhsic_port_power(ehci, 1); - writel_relaxed(1, hcd->regs + 0xb0); - writel_relaxed(0x1d4d, hcd->regs + 0x90); - writel_relaxed(0x4, hcd->regs + 0xa0); - dsb(); - break; - default: - break; - } -out: - return count; -} - -static DEVICE_ATTR(ehci_rkhsic_power, S_IRUGO | S_IWUSR, ehci_rkhsic_power_show, - ehci_rkhsic_power_store); - -static ssize_t hsic_debug_show(struct device *_dev, - struct device_attribute *attr, char *buf) -{ - volatile uint32_t *addr; - - HSIC_EHCI_PRINT("******** EHCI Capability Registers **********\n"); - addr = &g_hsic_ehci->caps->hc_capbase; - HSIC_EHCI_PRINT("HCIVERSION / CAPLENGTH @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = &g_hsic_ehci->caps->hcs_params; - HSIC_EHCI_PRINT("HCSPARAMS @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = &g_hsic_ehci->caps->hcc_params; - HSIC_EHCI_PRINT("HCCPARAMS @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - HSIC_EHCI_PRINT("********* EHCI Operational Registers *********\n"); - addr = &g_hsic_ehci->regs->command; - HSIC_EHCI_PRINT("USBCMD @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = &g_hsic_ehci->regs->status; - HSIC_EHCI_PRINT("USBSTS @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = &g_hsic_ehci->regs->intr_enable; - HSIC_EHCI_PRINT("USBINTR @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = &g_hsic_ehci->regs->frame_index; - HSIC_EHCI_PRINT("FRINDEX @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = &g_hsic_ehci->regs->segment; - HSIC_EHCI_PRINT("CTRLDSSEGMENT @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = &g_hsic_ehci->regs->frame_list; - HSIC_EHCI_PRINT("PERIODICLISTBASE @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = &g_hsic_ehci->regs->async_next; - HSIC_EHCI_PRINT("ASYNCLISTADDR @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = &g_hsic_ehci->regs->configured_flag; - HSIC_EHCI_PRINT("CONFIGFLAG @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - addr = g_hsic_ehci->regs->port_status; - HSIC_EHCI_PRINT("PORTSC @0x%08x: 0x%08x\n", - (uint32_t) addr, readl_relaxed(addr)); - return sprintf(buf, "HSIC_EHCI Registers Dump\n"); -} - -static DEVICE_ATTR(hsic_debug_ehci, S_IRUGO, hsic_debug_show, NULL); - -static struct of_device_id rk_hsic_of_match[] = { - { - .compatible = "rockchip,rk3188_rk_hsic_host", - .data = &rkhsic_pdata_rk3188, - }, - { - .compatible = "rockchip,rk3288_rk_hsic_host", - .data = &rkhsic_pdata_rk3288, - }, - {}, -}; - -MODULE_DEVICE_TABLE(of, rk_hsic_of_match); - -static int ehci_rkhsic_probe(struct platform_device *pdev) -{ - struct usb_hcd *hcd; - struct ehci_hcd *ehci; - struct resource *res; - struct device *dev = &pdev->dev; - struct rkehci_platform_data *pldata; - int ret; - int retval = 0; - static u64 usb_dmamask = 0xffffffffUL; - struct device_node *node = pdev->dev.of_node; - const struct of_device_id *match = - of_match_device(of_match_ptr(rk_hsic_of_match), &pdev->dev); - - dev_dbg(&pdev->dev, "ehci_rkhsic proble\n"); - - if (match && match->data) { - dev->platform_data = match->data; - } else { - dev_err(dev, "ehci_rkhsic match failed\n"); - return -EINVAL; - } - - pldata = dev->platform_data; - pldata->dev = dev; - - if (!node) { - dev_err(dev, "device node not found\n"); - return -EINVAL; - } - - dev->dma_mask = &usb_dmamask; - - retval = device_create_file(dev, &dev_attr_ehci_rkhsic_power); - retval = device_create_file(dev, &dev_attr_hsic_debug_ehci); - hcd = usb_create_hcd(&rk_hsic_driver, &pdev->dev, dev_name(&pdev->dev)); - if (!hcd) { - dev_err(&pdev->dev, "Unable to create HCD\n"); - return -ENOMEM; - } - - if (pldata->hw_init) - pldata->hw_init(); - - if (pldata->clock_init) { - pldata->clock_init(pldata); - pldata->clock_enable(pldata, 1); - } - - if (pldata->soft_reset) - pldata->soft_reset(pldata, RST_POR);; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "Unable to get memory resource\n"); - ret = -ENODEV; - goto put_hcd; - } - - hcd->rsrc_start = res->start; - hcd->rsrc_len = resource_size(res); - hcd->regs = devm_ioremap_resource(dev, res); - - if (!hcd->regs) { - dev_err(&pdev->dev, "ioremap failed\n"); - ret = -ENOMEM; - goto put_hcd; - } - - hcd->irq = platform_get_irq(pdev, 0); - if (hcd->irq < 0) { - dev_err(&pdev->dev, "Unable to get IRQ resource\n"); - ret = hcd->irq; - goto put_hcd; - } - - ehci = hcd_to_ehci(hcd); - ehci->caps = hcd->regs; - ehci->regs = hcd->regs + 0x10; - printk("%s %p %p\n", __func__, ehci->caps, ehci->regs); - - dbg_hcs_params(ehci, "reset"); - dbg_hcc_params(ehci, "reset"); - - ehci->hcs_params = readl(&ehci->caps->hcs_params); - - ret = usb_add_hcd(hcd, hcd->irq, IRQF_DISABLED | IRQF_SHARED); - if (ret) { - dev_err(&pdev->dev, "Failed to add USB HCD\n"); - goto put_hcd; - } - - g_hsic_ehci = ehci; - ehci_rkhsic_port_power(ehci, 1); - writel_relaxed(1, hcd->regs + 0xb0); - writel_relaxed(0x1d4d, hcd->regs + 0x90); - writel_relaxed(0x4, hcd->regs + 0xa0); - dsb(); - - printk("%s ok\n", __func__); - - return 0; - -put_hcd: - if (pldata->clock_enable) - pldata->clock_enable(pldata, 0); - usb_put_hcd(hcd); - - return ret; -} - -static int ehci_rkhsic_remove(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - - usb_put_hcd(hcd); - - return 0; -} - -#ifdef CONFIG_PM -static int ehci_rkhsic_pm_suspend(struct device *dev) -{ - struct usb_hcd *hcd = dev_get_drvdata(dev); - bool do_wakeup = device_may_wakeup(dev); - int ret; - - dev_dbg(dev, "ehci-rkhsic PM suspend\n"); - ret = ehci_suspend(hcd, do_wakeup); - - return ret; -} - -static int ehci_rkhsic_pm_resume(struct device *dev) -{ - struct usb_hcd *hcd = dev_get_drvdata(dev); - - dev_dbg(dev, "ehci-rkhsic PM resume\n"); - ehci_resume(hcd, false); - - return 0; -} -#else -#define ehci_rkhsic_pm_suspend NULL -#define ehci_rkhsic_pm_resume NULL -#endif - -static const struct dev_pm_ops ehci_rkhsic_dev_pm_ops = { - .suspend = ehci_rkhsic_pm_suspend, - .resume = ehci_rkhsic_pm_resume, -}; - -static struct platform_driver ehci_rkhsic_driver = { - .probe = ehci_rkhsic_probe, - .remove = ehci_rkhsic_remove, - .driver = { - .name = "rockchip_hsic_host", - .of_match_table = of_match_ptr(rk_hsic_of_match), -#ifdef CONFIG_PM - .pm = &ehci_rkhsic_dev_pm_ops, -#endif - }, -}; diff --git a/drivers/usb/host/ehci1-rockchip.c b/drivers/usb/host/ehci1-rockchip.c new file mode 100755 index 000000000000..b973947d7665 --- /dev/null +++ b/drivers/usb/host/ehci1-rockchip.c @@ -0,0 +1,376 @@ +/* ehci-msm.c - HSUSB Host Controller Driver Implementation + * + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. + * + * Partly derived from ehci-fsl.c and ehci-hcd.c + * Copyright (c) 2000-2004 by David Brownell + * Copyright (c) 2005 MontaVista Software + * + * All source code in this file is licensed under the following license except + * where indicated. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program; if not, you can find it at http://www.fsf.org + */ + +# include +# include +# include +# include +# include +# include +# include "ehci.h" +# include "../dwc_otg_310/usbdev_rk.h" + +static int rkehci1_status = 1; +static struct ehci_hcd *g_ehci; +#define EHCI1_PRINT(x...) printk(KERN_INFO "EHCI1: " x) + +static void ehci1_rk_port_power(struct ehci_hcd *ehci, int is_on) +{ + unsigned port; + + if (!HCS_PPC(ehci->hcs_params)) + return; + + ehci_dbg(ehci, "...power%s ports...\n", is_on ? "up" : "down"); + for (port = HCS_N_PORTS(ehci->hcs_params); port > 0;) + (void)ehci_hub_control(ehci_to_hcd(ehci), + is_on ? SetPortFeature : + ClearPortFeature, USB_PORT_FEAT_POWER, + port--, NULL, 0); + /* Flush those writes */ + ehci_readl(ehci, &ehci->regs->command); + msleep(20); +} + +static struct hc_driver rk_ehci1_driver = { + .description = hcd_name, + .product_desc = "Rockchip On-Chip EHCI1 Host Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ + .irq = ehci_irq, + .flags = HCD_USB2 | HCD_MEMORY, + + .reset = ehci_init, + .start = ehci_run, + + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + /* + * PM support + */ +#ifdef CONFIG_PM + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, +#endif +}; + +static ssize_t ehci1_rk_power_show(struct device *_dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", rkehci1_status); +} + +static ssize_t ehci1_rk_power_store(struct device *_dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + uint32_t val = simple_strtoul(buf, NULL, 16); + struct usb_hcd *hcd = dev_get_drvdata(_dev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct rkehci_platform_data *pldata = _dev->platform_data; + + printk("%s: %d setting to: %d\n", __func__, rkehci1_status, val); + if (val == rkehci1_status) + goto out; + + rkehci1_status = val; + switch (val) { + case 0: /* power down */ + ehci1_rk_port_power(ehci, 0); + writel_relaxed(0, hcd->regs + 0xb0); + dsb(); + msleep(5); + usb_remove_hcd(hcd); + break; + case 1: /* power on */ + pldata->soft_reset(pldata, RST_POR); + usb_add_hcd(hcd, hcd->irq, IRQF_DISABLED | IRQF_SHARED); + + ehci1_rk_port_power(ehci, 1); + writel_relaxed(1, hcd->regs + 0xb0); + writel_relaxed(0x1d4d, hcd->regs + 0x90); + writel_relaxed(0x4, hcd->regs + 0xa0); + dsb(); + break; + default: + break; + } +out: + return count; +} + +static DEVICE_ATTR(ehci1_rk_power, S_IRUGO | S_IWUSR, ehci1_rk_power_show, + ehci1_rk_power_store); + +static ssize_t ehci1_debug_show(struct device *_dev, + struct device_attribute *attr, char *buf) +{ + volatile uint32_t *addr; + + EHCI1_PRINT("******** EHCI Capability Registers **********\n"); + addr = &g_ehci->caps->hc_capbase; + EHCI1_PRINT("HCIVERSION / CAPLENGTH @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = &g_ehci->caps->hcs_params; + EHCI1_PRINT("HCSPARAMS @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = &g_ehci->caps->hcc_params; + EHCI1_PRINT("HCCPARAMS @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + EHCI1_PRINT("********* EHCI Operational Registers *********\n"); + addr = &g_ehci->regs->command; + EHCI1_PRINT("USBCMD @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = &g_ehci->regs->status; + EHCI1_PRINT("USBSTS @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = &g_ehci->regs->intr_enable; + EHCI1_PRINT("USBINTR @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = &g_ehci->regs->frame_index; + EHCI1_PRINT("FRINDEX @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = &g_ehci->regs->segment; + EHCI1_PRINT("CTRLDSSEGMENT @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = &g_ehci->regs->frame_list; + EHCI1_PRINT("PERIODICLISTBASE @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = &g_ehci->regs->async_next; + EHCI1_PRINT("ASYNCLISTADDR @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = &g_ehci->regs->configured_flag; + EHCI1_PRINT("CONFIGFLAG @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + addr = g_ehci->regs->port_status; + EHCI1_PRINT("PORTSC @0x%08x: 0x%08x\n", + (uint32_t) addr, readl_relaxed(addr)); + return sprintf(buf, "EHCI1 Registers Dump\n"); +} + +static DEVICE_ATTR(debug_ehci1, S_IRUGO, ehci1_debug_show, NULL); + +static struct of_device_id rk_ehci1_of_match[] = { + { + .compatible = "rockchip,rk3188_rk_ehci_host", + .data = &rkehci_pdata_rk3188, + }, + { + .compatible = "rockchip,rk3288_rk_ehci1_host", + .data = &rkehci1_pdata_rk3288, + }, + {}, +}; + +MODULE_DEVICE_TABLE(of, rk_ehci1_of_match); + +static int ehci1_rk_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct ehci_hcd *ehci; + struct resource *res; + struct device *dev = &pdev->dev; + struct rkehci_platform_data *pldata; + int ret; + int retval = 0; + static u64 usb_dmamask = 0xffffffffUL; + struct device_node *node = pdev->dev.of_node; + const struct of_device_id *match = + of_match_device(of_match_ptr(rk_ehci1_of_match), &pdev->dev); + + dev_dbg(&pdev->dev, "ehci1_rk proble\n"); + + if (match && match->data) { + dev->platform_data = (void *)match->data; + } else { + dev_err(dev, "ehci1_rk match failed\n"); + return -EINVAL; + } + + pldata = dev->platform_data; + pldata->dev = dev; + + if (!node) { + dev_err(dev, "device node not found\n"); + return -EINVAL; + } + + dev->dma_mask = &usb_dmamask; + + retval = device_create_file(dev, &dev_attr_ehci1_rk_power); + retval = device_create_file(dev, &dev_attr_debug_ehci1); + hcd = usb_create_hcd(&rk_ehci1_driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) { + dev_err(&pdev->dev, "Unable to create HCD\n"); + return -ENOMEM; + } + + if (pldata->hw_init) + pldata->hw_init(); + + if (pldata->clock_init) { + pldata->clock_init(pldata); + pldata->clock_enable(pldata, 1); + } + + if (pldata->soft_reset) + pldata->soft_reset(pldata, RST_POR);; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Unable to get memory resource\n"); + ret = -ENODEV; + goto put_hcd; + } + + hcd->rsrc_start = res->start; + hcd->rsrc_len = resource_size(res); + hcd->regs = devm_ioremap_resource(dev, res); + + if (!hcd->regs) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto put_hcd; + } + + hcd->irq = platform_get_irq(pdev, 0); + if (hcd->irq < 0) { + dev_err(&pdev->dev, "Unable to get IRQ resource\n"); + ret = hcd->irq; + goto put_hcd; + } + + ehci = hcd_to_ehci(hcd); + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + 0x10; + printk("%s %p %p\n", __func__, ehci->caps, ehci->regs); + + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + ehci->hcs_params = readl(&ehci->caps->hcs_params); + + ret = usb_add_hcd(hcd, hcd->irq, IRQF_DISABLED | IRQF_SHARED); + if (ret) { + dev_err(&pdev->dev, "Failed to add USB HCD\n"); + goto put_hcd; + } + + g_ehci = ehci; + ehci1_rk_port_power(ehci, 1); + writel_relaxed(1, hcd->regs + 0xb0); + writel_relaxed(0x1d4d, hcd->regs + 0x90); + writel_relaxed(0x4, hcd->regs + 0xa0); + dsb(); + + printk("%s ok\n", __func__); + + return 0; + +put_hcd: + if (pldata->clock_enable) + pldata->clock_enable(pldata, 0); + usb_put_hcd(hcd); + + return ret; +} + +static int ehci1_rk_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_put_hcd(hcd); + + return 0; +} + +#ifdef CONFIG_PM +static int ehci1_rk_pm_suspend(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + bool do_wakeup = device_may_wakeup(dev); + int ret; + + dev_dbg(dev, "ehci1-rockchip PM suspend\n"); + ret = ehci_suspend(hcd, do_wakeup); + + return ret; +} + +static int ehci1_rk_pm_resume(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + + dev_dbg(dev, "ehci1-rockchip PM resume\n"); + ehci_resume(hcd, false); + + return 0; +} +#else +#define ehci1_rk_pm_suspend NULL +#define ehci1_rk_pm_resume NULL +#endif + +static const struct dev_pm_ops ehci1_rk_dev_pm_ops = { + .suspend = ehci1_rk_pm_suspend, + .resume = ehci1_rk_pm_resume, +}; + +static struct platform_driver ehci1_rk_driver = { + .probe = ehci1_rk_probe, + .remove = ehci1_rk_remove, + .driver = { + .name = "rockchip_ehci1_host", + .of_match_table = of_match_ptr(rk_ehci1_of_match), +#ifdef CONFIG_PM + .pm = &ehci1_rk_dev_pm_ops, +#endif + }, +}; diff --git a/include/dt-bindings/clock/rockchip,rk3288.h b/include/dt-bindings/clock/rockchip,rk3288.h index 8b45948c45fb..1a2803c4f168 100644 --- a/include/dt-bindings/clock/rockchip,rk3288.h +++ b/include/dt-bindings/clock/rockchip,rk3288.h @@ -89,9 +89,9 @@ #define RK3288_SOFT_RST_4RES6 70 #define RK3288_SOFT_RST_CCP 71 #define RK3288_SOFT_RST_USB_HOST0 72 -#define RK3288_SOFT_RST_HSIC 73 -#define RK3288_SOFT_RST_HSIC_AUX 74 -#define RK3288_SOFT_RST_HSICPHY 75 +#define RK3288_SOFT_RST_EHCI1 73 +#define RK3288_SOFT_RST_EHCI1_AUX 74 +#define RK3288_SOFT_RST_EHCI1PHY 75 #define RK3288_SOFT_RST_HSADC 76 #define RK3288_SOFT_RST_NANDC0 77 #define RK3288_SOFT_RST_NANDC1 78 diff --git a/include/dt-bindings/clock/rockchip,rk3368.h b/include/dt-bindings/clock/rockchip,rk3368.h index 7b095f77a719..9ebf185d8941 100644 --- a/include/dt-bindings/clock/rockchip,rk3368.h +++ b/include/dt-bindings/clock/rockchip,rk3368.h @@ -81,9 +81,9 @@ #define RK3368_SRST_4RES6 70 #define RK3368_SRST_4RES7 71 #define RK3368_SRST_HOST0_H 72 -#define RK3368_SRST_HSIC 73 -#define RK3368_SRST_HSIC_AUX 74 -#define RK3368_SRST_HSICPHY 75 +#define RK3368_SRST_EHCI1 73 +#define RK3368_SRST_EHCI1_AUX 74 +#define RK3368_SRST_EHCI1PHY 75 #define RK3368_SRST_HSADC_H 76 #define RK3368_SRST_NANDC0 77 #define RK3368_SRST_4RES14 78 diff --git a/include/linux/rockchip/grf.h b/include/linux/rockchip/grf.h index d65094439804..8c47a0386dc9 100755 --- a/include/linux/rockchip/grf.h +++ b/include/linux/rockchip/grf.h @@ -79,7 +79,7 @@ #define RK3188_GRF_UOC3_CON0 0x0138 #define RK3188_GRF_UOC3_CON1 0x013c -#define RK3188_GRF_HSIC_STAT 0x0140 +#define RK3188_GRF_EHCI_STAT 0x0140 #define RK3188_GRF_OS_REG0 0x0144 #define RK3188_GRF_OS_REG1 0x0148 #define RK3188_GRF_OS_REG2 0x014c