From: chenxing <chenxing@rock-chips.com>
Date: Fri, 12 Jul 2013 07:47:26 +0000 (+0800)
Subject: rk3188: fix ddr pll do not update status
X-Git-Tag: firefly_0821_release~6892
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f75b8858cd16ffc729611faa64eeafdb727f7759;p=firefly-linux-kernel-4.4.55.git

rk3188: fix ddr pll do not update status
---

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index 2f010a80bc56..4a959ab9b22b 100755
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -1361,7 +1361,9 @@ static unsigned long ddr_clk_recalc_rate(struct clk *clk)
 	u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 	unsigned long rate = 0;
 	clk->parent = clk->get_parent(clk);
-	rate = clk->parent->recalc(clk->parent) >> shift;
+	clk->parent->rate = clk->parent->recalc(clk->parent);
+	rate = clk->parent->rate >> shift;
+
 	CLKDATA_DBG("%s new clock rate is %lu (shift %u), parent=%s, rate=%lu\n", 
 			clk->name, rate, shift, clk->parent->name, clk->parent->rate);
 	return rate;