From: Matthias Braun <matze@braunis.de>
Date: Tue, 19 May 2015 17:52:32 +0000 (+0000)
Subject: RegisterCoalescer: Improve a comment.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f7ad33bd8a49717c6ce358b2b806cbd2e1a482fa;p=oota-llvm.git

RegisterCoalescer: Improve a comment.

Explain the relation of the example to the variables in the code,
explain what bad behaviour the code avoids in this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237706 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp
index c2d1620c552..9c3d075ff0f 100644
--- a/lib/CodeGen/RegisterCoalescer.cpp
+++ b/lib/CodeGen/RegisterCoalescer.cpp
@@ -955,12 +955,11 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
   TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI);
   MachineInstr *NewMI = std::prev(MII);
 
-  // A situation like the following:
-  //     %vreg0:subX = instr           ; DefMI
-  //     %vregY      = copy %vreg:subX ; CopyMI
-  // does not need subregisters/regclass widening after rematerialization, just
-  // do:
-  //     %vregY = instr
+  // In a situation like the following:
+  //     %vreg0:subreg = instr              ; DefMI, subreg = DstIdx
+  //     %vreg1        = copy %vreg0:subreg ; CopyMI, SrcIdx = 0
+  // instead of widening %vreg1 to the register class of %vreg0 simply do:
+  //     %vreg1 = instr
   const TargetRegisterClass *NewRC = CP.getNewRC();
   if (DstIdx != 0) {
     MachineOperand &DefMO = NewMI->getOperand(0);