From: Linus Torvalds Date: Sat, 5 Apr 2014 22:29:04 +0000 (-0700) Subject: Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc X-Git-Tag: firefly_0821_release~176^2~4131 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f83ccb93585d1f472c30fa2bbb8b56c23dbdb506;p=firefly-linux-kernel-4.4.55.git Merge tag 'dt-3.15' of git://git./linux/kernel/git/arm/arm-soc Pull ARM SoC device tree changes from Arnd Bergmann: "A large part of the arm-soc patches are nowadays DT changes, adding support for new SoCs, boards and devices without changing kernel source. The plan is still to move the devicetree files out of the kernel tree and reduce the amount of churn going on here, but we keep finding reasons to delay doing that. Changes are really all over the place, with little sticking out particularly. We have contributions from a total of 116 people in this branch. Unfortunately, the size of this branch also causes a significant number of conflicts at the moment, typically when subsystem maintainers merge patches that change the driver at the same time as the dts files. In most cases this could be avoided because the dts changes are supposed to be compatible in both ways, and we are asking everyone to send ARM dts changes through our tree only" * tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits) dts: stmmac: Document the clocks property in the stmmac base document dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. ARM: STi: stih41x: Add support for the FSM Serial Flash Controller ARM: STi: stih416: Add support for the FSM Serial Flash Controller ARM: tegra: fix Dalmore pinctrl configuration ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND ARM: dts: Build all keystone dt blobs ARM: dts: keystone: Fix control register range for clktsip ARM: dts: keystone: Fix domain register range for clkfftc1 ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap ARM: dts: bcm21664: Add device tree files. ARM: DT: bcm21664: Device tree bindings ARM: efm32: properly namespace i2c location property ARM: efm32: fix unit address part in USART2 device nodes' names ARM: mvebu: Enable NAND controller in Armada 385-DB ARM: mvebu: Add support for NAND controller in Armada 38x SoC ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs ... --- f83ccb93585d1f472c30fa2bbb8b56c23dbdb506 diff --cc Documentation/devicetree/bindings/iio/adc/at91_adc.txt index 000000000000,82061c7e4fea..0f813dec5e08 mode 000000,100644..100644 --- a/Documentation/devicetree/bindings/iio/adc/at91_adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt @@@ -1,0 -1,82 +1,87 @@@ + * AT91's Analog to Digital Converter (ADC) + + Required properties: + - compatible: Should be "atmel,-adc" + can be "at91sam9260", "at91sam9g45" or "at91sam9x5" + - reg: Should contain ADC registers location and length + - interrupts: Should contain the IRQ line for the ADC ++ - clock-names: tuple listing input clock names. ++ Required elements: "adc_clk", "adc_op_clk". ++ - clocks: phandles to input clocks. + - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this + device + - atmel,adc-startup-time: Startup Time of the ADC in microseconds as + defined in the datasheet + - atmel,adc-vref: Reference voltage in millivolts for the conversions + - atmel,adc-res: List of resolutions in bits supported by the ADC. List size + must be two at least. + - atmel,adc-res-names: Contains one identifier string for each resolution + in atmel,adc-res property. "lowres" and "highres" + identifiers are required. + + Optional properties: + - atmel,adc-use-external-triggers: Boolean to enable the external triggers + - atmel,adc-use-res: String corresponding to an identifier from + atmel,adc-res-names property. If not specified, the highest + resolution will be used. + - atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion + - atmel,adc-sample-hold-time: Sample and Hold Time in microseconds + - atmel,adc-ts-wires: Number of touchscreen wires. Should be 4 or 5. If this + value is set, then the adc driver will enable touchscreen + support. + NOTE: when adc touchscreen is enabled, the adc hardware trigger will be + disabled. Since touchscreen will occupy the trigger register. + - atmel,adc-ts-pressure-threshold: a pressure threshold for touchscreen. It + makes touch detection more precise. + + Optional trigger Nodes: + - Required properties: + * trigger-name: Name of the trigger exposed to the user + * trigger-value: Value to put in the Trigger register + to activate this trigger + - Optional properties: + * trigger-external: Is the trigger an external trigger? + + Examples: + adc0: adc@fffb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9260-adc"; + reg = <0xfffb0000 0x100>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; ++ clocks = <&adc_clk>, <&adc_op_clk>; ++ clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-channels-used = <0xff>; + atmel,adc-startup-time = <40>; + atmel,adc-use-external-triggers; + atmel,adc-vref = <3300>; + atmel,adc-res = <8 10>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-use-res = "lowres"; + + trigger@0 { + reg = <0>; + trigger-name = "external-rising"; + trigger-value = <0x1>; + trigger-external; + }; + trigger@1 { + reg = <1>; + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; + }; + + trigger@2 { + reg = <2>; + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; + }; + + trigger@3 { + reg = <3>; + trigger-name = "continuous"; + trigger-value = <0x6>; + }; + }; diff --cc Documentation/devicetree/bindings/net/stmmac.txt index 5748351fb9df,9a0c1b7bee29..80c1fb8bfbb8 --- a/Documentation/devicetree/bindings/net/stmmac.txt +++ b/Documentation/devicetree/bindings/net/stmmac.txt @@@ -30,7 -31,13 +30,11 @@@ Optional properties - resets: Should contain a phandle to the STMMAC reset signal, if any - reset-names: Should contain the reset signal name "stmmaceth", if a reset phandle is given -- max-frame-size: Maximum Transfer Unit (IEEE defined MTU), rather - than the maximum frame size. +- max-frame-size: See ethernet.txt file in the same directory + - clocks: If present, the first clock should be the GMAC main clock, + further clocks may be specified in derived bindings. + - clocks-names: One name for each entry in the clocks property, the + first one should be "stmmaceth". Examples: diff --cc Documentation/devicetree/bindings/vendor-prefixes.txt index 95465d57eb31,4685ec396c34..0f01c9bf19c8 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@@ -30,11 -26,10 +30,12 @@@ chrp Common Hardware Reference Platfor chunghwa Chunghwa Picture Tubes Ltd. cirrus Cirrus Logic, Inc. cortina Cortina Systems, Inc. +crystalfontz Crystalfontz America, Inc. dallas Maxim Integrated Products (formerly Dallas Semiconductor) davicom DAVICOM Semiconductor, Inc. +dlink D-Link Systems, Inc. denx Denx Software Engineering + dmo Data Modul AG edt Emerging Display Technologies emmicro EM Microelectronic epfl Ecole Polytechnique FÃ©dÃ©rale de Lausanne @@@ -94,8 -83,8 +98,9 @@@ schindler Schindle sil Silicon Image silabs Silicon Laboratories simtek + sii Seiko Instruments, Inc. sirf SiRF Technology, Inc. +smsc Standard Microsystems Corporation snps Synopsys, Inc. spansion Spansion Inc. st STMicroelectronics diff --cc arch/arm/boot/dts/Makefile index 112813a80b71,4bf43375eb90..35c146f31e46 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@@ -329,8 -381,31 +385,31 @@@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv0 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc706.dtb \ zynq-zed.dtb + dtb-$(CONFIG_MACH_ARMADA_370) += \ + armada-370-db.dtb \ + armada-370-mirabox.dtb \ + armada-370-netgear-rn102.dtb \ + armada-370-netgear-rn104.dtb \ + armada-370-rd.dtb + dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb + dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-db.dtb \ + armada-385-rd.dtb + dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-axpwifiap.dtb \ + armada-xp-db.dtb \ + armada-xp-gp.dtb \ + armada-xp-netgear-rn2120.dtb \ + armada-xp-matrix.dtb \ + armada-xp-openblocks-ax3-4.dtb + dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ + dove-cubox.dtb \ + dove-d2plug.dtb \ + dove-d3plug.dtb \ + dove-dove-db.dtb -targets += dtbs +targets += dtbs dtbs_install targets += $(dtb-y) endif diff --cc arch/arm/boot/dts/imx51-apf51dev.dts index d3f98141462c,c29cfa927c98..c5a9a24c280a --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts @@@ -18,9 -18,10 +18,9 @@@ display@di1 { compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 0>; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1_1>; + pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { lw700 { @@@ -125,9 -122,81 +127,85 @@@ MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 >; }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 + MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 + MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed + MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + >; + }; }; }; + +&ipu_di0_disp0 { + remote-endpoint = <&display_in>; +}; diff --cc arch/arm/boot/dts/imx51-babbage.dts index 671927145632,121dadd125c0..9e9deb244b76 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@@ -21,11 -21,12 +21,11 @@@ reg = <0x90000000 0x20000000>; }; - display@di0 { + display0: display@di0 { compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 0>; interface-pix-fmt = "rgb24"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1_1>; + pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { native-mode = <&timing0>; timing0: dvi { @@@ -40,19 -41,14 +40,19 @@@ vsync-len = <10>; }; }; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; }; - display@di1 { + display1: display@di1 { compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 1>; interface-pix-fmt = "rgb565"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp2_1>; + pinctrl-0 = <&pinctrl_ipu_disp2>; status = "disabled"; display-timings { native-mode = <&timing1>; diff --cc arch/arm/boot/dts/imx51.dtsi index 28c96aada80b,e4b07d1a9a56..5f8216d08f6b --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@@ -102,23 -118,11 +124,25 @@@ compatible = "fsl,imx51-ipu"; reg = <0x40000000 0x20000000>; interrupts = <11 10>; - clocks = <&clks 59>, <&clks 110>, <&clks 61>; + clocks = <&clks IMX5_CLK_IPU_GATE>, + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; + + ipu_di0: port@2 { + reg = <2>; + + ipu_di0_disp0: endpoint { + }; + }; + + ipu_di1: port@3 { + reg = <3>; + + ipu_di1_disp1: endpoint { + }; + }; }; aips@70000000 { /* AIPS1 */ diff --cc arch/arm/boot/dts/imx53-m53evk.dts index 0298adc73bb7,e8d11e2a93cd..f6d3ac3e5587 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@@ -21,11 -21,12 +21,11 @@@ }; soc { - display@di1 { + display1: display@di1 { compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 1>; interface-pix-fmt = "bgr666"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp2_1>; + pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { 800x480p60 { @@@ -226,13 -400,9 +405,13 @@@ }; }; +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + &nfc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand_1>; + pinctrl-0 = <&pinctrl_nand>; nand-bus-width = <8>; nand-ecc-mode = "hw"; status = "okay"; diff --cc arch/arm/boot/dts/imx53-mba53.dts index a5b55c603591,55af11037a00..7c8c12969892 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts @@@ -38,22 -30,32 +30,37 @@@ compatible = "fsl,imx-parallel-display"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp1_1>; - crtcs = <&ipu 1>; interface-pix-fmt = "rgb24"; status = "disabled"; + + port { + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; }; - reg_3p2v: 3p2v { - compatible = "regulator-fixed"; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_backlight: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "lcd-supply"; + gpio = <&gpio2 5 0>; + startup-delay-us = <5000>; + }; + + reg_3p2v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; }; sound { diff --cc arch/arm/boot/dts/imx53-qsb-common.dtsi index 000000000000,2dca98b79f48..3f825a6813da mode 000000,100644..100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@@ -1,0 -1,336 +1,345 @@@ + /* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + #include "imx53.dtsi" + + / { + memory { + reg = <0x70000000 0x40000000>; + }; + - display@di0 { ++ display0: display@di0 { + compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 0>; + interface-pix-fmt = "rgb565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp0>; + status = "disabled"; + display-timings { + claawvga { + native-mode; + clock-frequency = <27000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <60>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; ++ ++ port { ++ display0_in: endpoint { ++ remote-endpoint = <&ipu_di0_disp0>; ++ }; ++ }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power Button"; + gpios = <&gpio1 8 0>; + linux,code = <116>; /* KEY_POWER */ + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio2 14 0>; + linux,code = <115>; /* KEY_VOLUMEUP */ + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio2 15 0>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio7_7>; + + user { + label = "Heartbeat"; + gpios = <&gpio7 7 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_usb_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 8 0>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx53-qsb-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx53-qsb-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + }; + + &esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; + }; + ++&ipu_di0_disp0 { ++ remote-endpoint = <&display0_in>; ++}; ++ + &ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; + }; + + &esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; + bus-width = <8>; + status = "okay"; + }; + + &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-qsb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_GPIO_8__GPIO1_8 0x80000000 + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 + MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 + MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 + MX53_PAD_GPIO_16__GPIO7_11 0x80000000 + >; + }; + + led_pin_gpio7_7: led_gpio7_7@0 { + fsl,pins = < + MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 + MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_ipu_disp0: ipudisp0grp { + fsl,pins = < + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 + >; + }; + }; + }; + + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + }; + + &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p2v>; + VDDIO-supply = <®_3p2v>; + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; + }; + }; + + &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + }; + + &audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + }; + + &fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; + }; + + &sata { + status = "okay"; + }; + + &vpu { + status = "okay"; + }; + + &usbh1 { + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + status = "okay"; + }; + + &usbotg { + dr_mode = "peripheral"; + status = "okay"; + }; diff --cc arch/arm/boot/dts/imx53.dtsi index 04d3127edfe1,80615dfa2177..b57ab57740f6 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@@ -89,50 -91,27 +96,63 @@@ interrupt-parent = <&tzic>; ranges; + sata: sata@10000000 { + compatible = "fsl,imx53-ahci"; + reg = <0x10000000 0x1000>; + interrupts = <28>; + clocks = <&clks IMX5_CLK_SATA_GATE>, + <&clks IMX5_CLK_SATA_REF>, + <&clks IMX5_CLK_AHB>; + clock-names = "sata_gate", "sata_ref", "ahb"; + status = "disabled"; + }; + ipu: ipu@18000000 { - #crtc-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; compatible = "fsl,imx53-ipu"; reg = <0x18000000 0x080000000>; interrupts = <11 10>; - clocks = <&clks 59>, <&clks 110>, <&clks 61>; + clocks = <&clks IMX5_CLK_IPU_GATE>, + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; + + ipu_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu_di0_disp0: endpoint@0 { + reg = <0>; + }; + + ipu_di0_lvds0: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds0_in>; + }; + }; + + ipu_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu_di1_disp1: endpoint@0 { + reg = <0>; + }; + + ipu_di1_lvds1: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds1_in>; + }; + + ipu_di1_tve: endpoint@2 { + reg = <2>; + remote-endpoint = <&tve_in>; + }; + }; }; aips@50000000 { /* AIPS1 */ @@@ -1152,15 -652,11 +703,16 @@@ compatible = "fsl,imx53-tve"; reg = <0x63ff0000 0x1000>; interrupts = <92>; - clocks = <&clks 69>, <&clks 116>; + clocks = <&clks IMX5_CLK_TVE_GATE>, + <&clks IMX5_CLK_IPU_DI1_SEL>; clock-names = "tve", "di_sel"; - crtcs = <&ipu 1>; status = "disabled"; + + port { + tve_in: endpoint { + remote-endpoint = <&ipu_di1_tve>; + }; + }; }; vpu: vpu@63ff4000 { diff --cc arch/arm/boot/dts/imx6q.dtsi index 2a8d9de666c9,fadf4981c0ca..addd3f881ce2 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@@ -132,11 -146,11 +146,12 @@@ }; ipu2: ipu@02800000 { - #crtc-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; compatible = "fsl,imx6q-ipu"; reg = <0x02800000 0x400000>; - interrupts = <0 8 0x4 0 7 0x4>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 133>, <&clks 134>, <&clks 137>; clock-names = "bus", "di0", "di1"; resets = <&src 4>; diff --cc arch/arm/boot/dts/imx6qdl.dtsi index 64a8cbe9480f,947e463a2b2f..55cb926fa3f7 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@@ -1716,11 -945,11 +1027,12 @@@ }; ipu1: ipu@02400000 { - #crtc-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; compatible = "fsl,imx6q-ipu"; reg = <0x02400000 0x400000>; - interrupts = <0 6 0x4 0 5 0x4>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, + <0 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 130>, <&clks 131>, <&clks 132>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; diff --cc arch/arm/boot/dts/qcom-msm8960.dtsi index 3a9c3caa9aad,ecfba7254205..997b7b94e117 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@@ -9,12 -9,36 +9,42 @@@ compatible = "qcom,msm8960"; interrupt-parent = <&intc>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 14 0x304>; + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + qcom,no-pc-write; + }; + intc: interrupt-controller@2000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; diff --cc arch/arm/boot/dts/qcom-msm8974.dtsi index 1eff4130cde0,011eb0937e58..f68723918b3f --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@@ -9,11 -9,49 +9,54 @@@ compatible = "qcom,msm8974"; interrupt-parent = <&intc>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 9 0xf04>; + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + }; + + cpu@2 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + }; + + cpu@3 { + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + qcom,saw = <&saw_l2>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 7 0xf04>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; diff --cc arch/arm/boot/dts/sun4i-a10.dtsi index 9321681cc45a,6af23323e18c..9174724571e2 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@@ -330,8 -377,90 +377,90 @@@ #size-cells = <0>; }; + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; + reg-names = "phy_ctrl", "pmu1", "pmu2"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 1>, <&usb_clk 2>; + reset-names = "usb1_reset", "usb2_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <64>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@01c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <56>; + clocks = <&pll6 0>, <&ahb_gates 25>; + status = "disabled"; + }; + + ehci1: usb@01c1c000 { + compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <40>; + clocks = <&ahb_gates 3>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1c400 { + compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <65>; + clocks = <&usb_clk 7>, <&ahb_gates 4>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + spi3: spi@01c1f000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = <50>; + clocks = <&ahb_gates 23>, <&spi3_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-ic"; + compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; diff --cc arch/arm/boot/dts/sun5i-a10s.dtsi index ee17b1c379e3,8681f6c18fdc..79989ed5658d --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@@ -293,8 -338,51 +338,51 @@@ #size-cells = <0>; }; + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 1>; + reset-names = "usb1_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <40>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-ic"; + compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; diff --cc arch/arm/boot/dts/sun5i-a13.dtsi index 3490ef9ec603,7c6bb1bde9dd..f01c315bdc4b --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@@ -274,8 -298,73 +298,73 @@@ #size-cells = <1>; ranges; + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 1>; + reset-names = "usb1_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <40>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-ic"; + compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; diff --cc arch/arm/boot/dts/sun7i-a20.dtsi index cadcf2f9881d,dadb3812342f..32efc105df83 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@@ -339,14 -401,28 +401,36 @@@ #size-cells = <1>; ranges; + nmi_intc: interrupt-controller@01c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupts = <0 0 4>; + }; + + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <0 10 4>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <0 11 4>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@01c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; diff --cc arch/arm/mach-omap2/pdata-quirks.c index c33e07e2f0d4,db242c483dc0..b04c5f0fc278 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@@ -22,8 -23,7 +23,9 @@@ #include "common-board-devices.h" #include "dss-common.h" #include "control.h" + #include "omap_device.h" +#include "omap-secure.h" +#include "soc.h" struct pdata_init { const char *compatible; @@@ -172,21 -188,42 +190,58 @@@ static void __init am35xx_emac_reset(vo omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ } + static struct gpio cm_t3517_wlan_gpios[] __initdata = { + { 56, GPIOF_OUT_INIT_HIGH, "wlan pwr" }, + { 4, GPIOF_OUT_INIT_HIGH, "xcvr noe" }, + }; + + static void __init omap3_sbc_t3517_wifi_init(void) + { + int err = gpio_request_array(cm_t3517_wlan_gpios, + ARRAY_SIZE(cm_t3517_wlan_gpios)); + if (err) { + pr_err("SBC-T3517: wl12xx gpios request failed: %d\n", err); + return; + } + + gpio_export(cm_t3517_wlan_gpios[0].gpio, 0); + gpio_export(cm_t3517_wlan_gpios[1].gpio, 0); + + msleep(100); + gpio_set_value(cm_t3517_wlan_gpios[1].gpio, 0); + } + + static void __init omap3_sbc_t3517_legacy_init(void) + { + omap3_sbc_t3x_usb_hub_init(152, "cm-t3517 usb hub"); + omap3_sbc_t3x_usb_hub_init(98, "sb-t35 usb hub"); + am35xx_emac_reset(); + hsmmc2_internal_input_clk(); + omap3_sbc_t3517_wifi_init(); + legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 145); + omap_ads7846_init(1, 57, 0, NULL); + } + + static void __init am3517_evm_legacy_init(void) + { + am35xx_emac_reset(); + } ++ +static void __init nokia_n900_legacy_init(void) +{ + hsmmc2_internal_input_clk(); + + if (omap_type() == OMAP2_DEVICE_TYPE_SEC) { + if (IS_ENABLED(CONFIG_ARM_ERRATA_430973)) { + pr_info("RX-51: Enabling ARM errata 430973 workaround\n"); + /* set IBE to 1 */ + rx51_secure_update_aux_cr(BIT(6), 0); + } else { + pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n"); + pr_warning("Thumb binaries may crash randomly without this workaround\n"); + } + } +} #endif /* CONFIG_ARCH_OMAP3 */ #ifdef CONFIG_ARCH_OMAP4 @@@ -257,8 -307,9 +325,10 @@@ struct of_dev_auxdata omap_auxdata_look #endif #ifdef CONFIG_ARCH_OMAP3 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), + OF_DEV_AUXDATA("ti,omap3-padconf", 0x480025a0, "480025a0.pinmux", &pcs_pdata), OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), + OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu", + &omap3_iommu_pdata), /* Only on am3517 */ OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL), OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0", @@@ -277,8 -334,10 +353,10 @@@ */ static struct pdata_init pdata_quirks[] __initdata = { #ifdef CONFIG_ARCH_OMAP3 + { "compulab,omap3-sbc-t3517", omap3_sbc_t3517_legacy_init, }, + { "compulab,omap3-sbc-t3530", omap3_sbc_t3530_legacy_init, }, { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, }, - { "nokia,omap3-n900", hsmmc2_internal_input_clk, }, + { "nokia,omap3-n900", nokia_n900_legacy_init, }, { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },