From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 26 Nov 2014 18:18:28 +0000 (+0000)
Subject: R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f87cce15403d8ee61ed912b30b7c79e795bf6c03;p=oota-llvm.git

R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies

This fixes moving boolean constants into registers before operating
on them. They get permuted and shrunk down to e32 anyway later. This
is a temporary fix until the patch that removes these pseudos is
committed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222844 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SILowerI1Copies.cpp b/lib/Target/R600/SILowerI1Copies.cpp
index 65b892cf122..226a672b343 100644
--- a/lib/Target/R600/SILowerI1Copies.cpp
+++ b/lib/Target/R600/SILowerI1Copies.cpp
@@ -93,19 +93,19 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
 
       if (MI.getOpcode() == AMDGPU::V_AND_I1) {
         I1Defs.push_back(MI.getOperand(0).getReg());
-        MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32));
+        MI.setDesc(TII->get(AMDGPU::V_AND_B32_e64));
         continue;
       }
 
       if (MI.getOpcode() == AMDGPU::V_OR_I1) {
         I1Defs.push_back(MI.getOperand(0).getReg());
-        MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32));
+        MI.setDesc(TII->get(AMDGPU::V_OR_B32_e64));
         continue;
       }
 
       if (MI.getOpcode() == AMDGPU::V_XOR_I1) {
         I1Defs.push_back(MI.getOperand(0).getReg());
-        MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32));
+        MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e64));
         continue;
       }