From: Nate Begeman Date: Fri, 15 Apr 2005 22:12:16 +0000 (+0000) Subject: Make pattern isel default for ppc X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f8b02949e3d13e9b7cd38e029fcbf3e799366aa7;p=oota-llvm.git Make pattern isel default for ppc Add new ppc beta option related to using condition registers Make pattern isel control flag (-enable-pattern-isel) global and tristate 0 == off 1 == on 2 == target default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h index 887e404f74e..a4038430cb3 100644 --- a/include/llvm/Target/TargetOptions.h +++ b/include/llvm/Target/TargetOptions.h @@ -34,6 +34,13 @@ namespace llvm { /// over the place. extern bool NoExcessFPPrecision; + /// PatternISelTriState - This flag is enabled when -pattern-isel=X is + /// specified on the command line. The default value is 2, in which case the + /// target chooses what is best for it. Setting X to 0 forces the use of + /// a simple ISel if available, while setting it to 1 forces the use of a + /// pattern ISel if available. + extern int PatternISelTriState; + } // End llvm namespace #endif diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h index ddda03c0f39..b2c60380621 100644 --- a/lib/Target/PowerPC/PPC.h +++ b/lib/Target/PowerPC/PPC.h @@ -29,6 +29,7 @@ FunctionPass *createPPC64ISelPattern(TargetMachine &TM); FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM); FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM); +extern bool PPCCRopts; } // end namespace llvm; // GCC #defines PPC on Linux but we use it as our namespace name diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 8430970e67d..6fe2c4ccbfe 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -1067,7 +1067,7 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) { BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2); } } else { -#if 0 + if (PPCCRopts) if (CC.getOpcode() == ISD::AND || CC.getOpcode() == ISD::OR) if (CC.getOperand(0).Val->hasOneUse() && CC.getOperand(1).Val->hasOneUse()) { @@ -1093,7 +1093,6 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) { return Result; } } -#endif Opc = PPC::BNE; Tmp1 = SelectExpr(CC); BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0); @@ -1127,7 +1126,7 @@ void ISel::SelectBranchCC(SDOperand N) unsigned Opc, CCReg; Select(N.getOperand(0)); //chain CCReg = SelectCC(N.getOperand(1), Opc); - + // Iterate to the next basic block, unless we're already at the end of the ilist::iterator It = BB, E = BB->getParent()->end(); if (++It == E) It = BB; diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 3d27c98e6af..6286735603e 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -30,15 +30,18 @@ using namespace llvm; namespace llvm { + bool PPCCRopts; cl::opt AIX("aix", cl::desc("Generate AIX/xcoff instead of Darwin/MachO"), cl::Hidden); - cl::opt EnablePPCLSR("enable-lsr-for-ppc", - cl::desc("Enable LSR for PPC (beta option!)"), + cl::desc("Enable LSR for PPC (beta)"), cl::Hidden); - cl::opt EnablePatternISel("enable-ppc-pattern-isel", cl::Hidden, - cl::desc("Enable the pattern isel")); + cl::opt EnablePPCCRopts("enable-cc-opts", + cl::desc("Enable opts using condition regs (beta)"), + cl::location(PPCCRopts), + cl::init(false), + cl::Hidden); } namespace { @@ -96,12 +99,13 @@ bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM, // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); + // Default to pattern ISel if (LP64) PM.add(createPPC64ISelPattern(*this)); - else if (EnablePatternISel) - PM.add(createPPC32ISelPattern(*this)); - else + else if (PatternISelTriState == 0) PM.add(createPPC32ISelSimple(*this)); + else + PM.add(createPPC32ISelPattern(*this)); if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(&std::cerr)); @@ -126,6 +130,8 @@ bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM, } void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) { + bool LP64 = (0 != dynamic_cast(&TM)); + if (EnablePPCLSR) { PM.add(createLoopStrengthReducePass()); PM.add(createCFGSimplificationPass()); @@ -145,7 +151,14 @@ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) { // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); - PM.add(createPPC32ISelSimple(TM)); + // Default to pattern ISel + if (LP64) + PM.add(createPPC64ISelPattern(TM)); + else if (PatternISelTriState == 0) + PM.add(createPPC32ISelSimple(TM)); + else + PM.add(createPPC32ISelPattern(TM)); + PM.add(createRegisterAllocator()); PM.add(createPrologEpilogCodeInserter()); diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp index 22df91faeb8..fc7530addda 100644 --- a/lib/Target/TargetMachine.cpp +++ b/lib/Target/TargetMachine.cpp @@ -25,6 +25,7 @@ namespace llvm { bool PrintMachineCode; bool NoFramePointerElim; bool NoExcessFPPrecision; + int PatternISelTriState; }; namespace { cl::opt PrintCode("print-machineinstrs", @@ -38,9 +39,13 @@ namespace { cl::init(false)); cl::opt DisableExcessPrecision("disable-excess-fp-precision", - cl::desc("Disable optimizations that may increase FP precision"), - cl::location(NoExcessFPPrecision), - cl::init(false)); + cl::desc("Disable optimizations that may increase FP precision"), + cl::location(NoExcessFPPrecision), + cl::init(false)); + cl::opt PatternISel("enable-pattern-isel", + cl::desc("sets the pattern ISel off(0), on(1), default(2)"), + cl::location(PatternISelTriState), + cl::init(2)); }; //--------------------------------------------------------------------------- diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index daa97b2464a..aa6de9c7b26 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -41,9 +41,6 @@ namespace { cl::opt DisableOutput("disable-x86-llc-output", cl::Hidden, cl::desc("Disable the X86 asm printer, for use " "when profiling the code generator.")); - cl::opt DisablePatternISel("disable-pattern-isel", cl::Hidden, - cl::desc("Disable the pattern isel XXX FIXME"), - cl::init(true)); #if 0 // FIXME: This should eventually be handled with target triples and @@ -113,7 +110,8 @@ bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM, // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); - if (DisablePatternISel) + // Default to simple ISel + if (PatternISelTriState != 1) PM.add(createX86SimpleInstructionSelector(*this)); else PM.add(createX86PatternInstructionSelector(*this)); @@ -171,7 +169,8 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) { // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); - if (DisablePatternISel) + // Default to simple ISel + if (PatternISelTriState != 1) PM.add(createX86SimpleInstructionSelector(TM)); else PM.add(createX86PatternInstructionSelector(TM));