From: 陈亮 Date: Fri, 28 Feb 2014 08:40:56 +0000 (-0800) Subject: rk3188:linux3.10: add ddr clk node ops X-Git-Tag: firefly_0821_release~6242 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f949ee0174145d9f2a9b8ad95107c24ffd914d72;p=firefly-linux-kernel-4.4.55.git rk3188:linux3.10: add ddr clk node ops --- diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi index 72c6e7312ca1..69be6dfd2203 100755 --- a/arch/arm/boot/dts/rk3188-clocks.dtsi +++ b/arch/arm/boot/dts/rk3188-clocks.dtsi @@ -852,6 +852,7 @@ clocks = <&clk_ddr>; clock-output-names = "clk_ddr"; rockchip,div-type = ; + rockchip,clkops-idx = ; #clock-cells = <0>; }; @@ -863,6 +864,8 @@ clocks = <&clk_dpll>, <&clk_gates1 7>; clock-output-names = "clk_ddr"; + rockchip,flags = <(CLK_GET_RATE_NOCACHE | + CLK_SET_RATE_NO_REPARENT)>; #clock-cells = <0>; }; diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c index 681ec552063f..73a19d59c911 100644 --- a/drivers/clk/rockchip/clk-ops.c +++ b/drivers/clk/rockchip/clk-ops.c @@ -8,6 +8,7 @@ #include #include "clk-ops.h" +#include "../../../arch/arm/mach-rockchip/common.h" @@ -408,6 +409,74 @@ const struct clk_ops clkops_rate_core_peri = { .set_rate = NULL, }; +static unsigned long clk_ddr_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* Same as clk_core, we should NOT set clk_ddr's parent + * (dpll) rate directly as a side effect. + */ + return clk_core_recalc_rate(hw, parent_rate); +} + +static long clk_ddr_determine_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *best_parent_rate, + struct clk **best_parent_p) +{ + long best = 0; + + if (!ddr_round_rate) { + /* Do nothing before ddr init */ + best = __clk_get_rate(hw->clk); + } else { + /* Func provided by ddr driver */ + best = ddr_round_rate(rate/MHZ) * MHZ; + } + + clk_debug("%s: from %lu to %lu\n", __func__, rate, best); + + return best; +} + +static long clk_ddr_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + return clk_ddr_determine_rate(hw, rate, prate, NULL); +} + +static int clk_ddr_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk *parent = __clk_get_parent(hw->clk); + struct clk *grand_p = __clk_get_parent(parent); + + + /* Do nothing before ddr init */ + if (!ddr_change_freq) + return 0; + + if (IS_ERR_OR_NULL(parent) || IS_ERR_OR_NULL(grand_p)) { + clk_err("fail to get parent or grand_parent!\n"); + return -EINVAL; + } + + clk_debug("%s: will set rate = %lu\n", __func__, rate); + + /* Func provided by ddr driver */ + ddr_change_freq(rate/MHZ); + + parent->rate = parent->ops->recalc_rate(parent->hw, + __clk_get_rate(grand_p)); + + return 0; +} + +const struct clk_ops clkops_rate_ddr = { + .recalc_rate = clk_ddr_recalc_rate, + .round_rate = clk_ddr_round_rate, + .set_rate = clk_ddr_set_rate, + .determine_rate = clk_ddr_determine_rate, +}; + struct clk_ops_table rk_clkops_rate_table[] = { {.index = CLKOPS_RATE_MUX_DIV, .clk_ops = &clkops_rate_auto_parent}, {.index = CLKOPS_RATE_EVENDIV, .clk_ops = &clkops_rate_evendiv}, @@ -416,6 +485,7 @@ struct clk_ops_table rk_clkops_rate_table[] = { {.index = CLKOPS_RATE_FRAC, .clk_ops = &clkops_rate_frac}, {.index = CLKOPS_RATE_CORE, .clk_ops = &clkops_rate_core}, {.index = CLKOPS_RATE_CORE_PERI, .clk_ops = &clkops_rate_core_peri}, + {.index = CLKOPS_RATE_DDR, .clk_ops = &clkops_rate_ddr}, {.index = CLKOPS_RATE_I2S, .clk_ops = NULL}, {.index = CLKOPS_RATE_CIFOUT, .clk_ops = NULL}, {.index = CLKOPS_RATE_UART, .clk_ops = NULL}, diff --git a/include/dt-bindings/clock/ddr.h b/include/dt-bindings/clock/ddr.h new file mode 100644 index 000000000000..66b06071c5a3 --- /dev/null +++ b/include/dt-bindings/clock/ddr.h @@ -0,0 +1,63 @@ +/* + * + * Copyright (C) 2011-2014 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_ROCKCHIP_DDR_H +#define __MACH_ROCKCHIP_DDR_H + +#define DDR3_800D (0) // 5-5-5 +#define DDR3_800E (1) // 6-6-6 +#define DDR3_1066E (2) // 6-6-6 +#define DDR3_1066F (3) // 7-7-7 +#define DDR3_1066G (4) // 8-8-8 +#define DDR3_1333F (5) // 7-7-7 +#define DDR3_1333G (6) // 8-8-8 +#define DDR3_1333H (7) // 9-9-9 +#define DDR3_1333J (8) // 10-10-10 +#define DDR3_1600G (9) // 8-8-8 +#define DDR3_1600H (10) // 9-9-9 +#define DDR3_1600J (11) // 10-10-10 +#define DDR3_1600K (12) // 11-11-11 +#define DDR3_1866J (13) // 10-10-10 +#define DDR3_1866K (14) // 11-11-11 +#define DDR3_1866L (15) // 12-12-12 +#define DDR3_1866M (16) // 13-13-13 +#define DDR3_2133K (17) // 11-11-11 +#define DDR3_2133L (18) // 12-12-12 +#define DDR3_2133M (19) // 13-13-13 +#define DDR3_2133N (20) // 14-14-14 +#define DDR3_DEFAULT (21) +#define DDR_DDR2 (22) +#define DDR_LPDDR (23) +#define DDR_LPDDR2 (24) + +#define PAUSE_CPU_STACK_SZIE 16 + +#define SYS_STATUS_NORMAL (1<<0) +#define SYS_STATUS_SUSPEND (1<<1) +#define SYS_STATUS_IDLE (1<<2) +#define SYS_STATUS_REBOOT (1<<3) +#define SYS_STATUS_VIDEO_720P (1<<4) +#define SYS_STATUS_VIDEO_1080P (1<<5) +#define SYS_STATUS_GPU (1<<6) +#define SYS_STATUS_RGA (1<<7) +#define SYS_STATUS_CIF0 (1<<8) +#define SYS_STATUS_CIF1 (1<<9) +#define SYS_STATUS_LCDC0 (1<<10) +#define SYS_STATUS_LCDC1 (1<<11) + +#define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_720P|SYS_STATUS_VIDEO_1080P) +#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0|SYS_STATUS_LCDC1) + +#endif diff --git a/include/dt-bindings/clock/rockchip,rk3188.h b/include/dt-bindings/clock/rockchip,rk3188.h index 302c959f755e..fc8edee528ef 100644 --- a/include/dt-bindings/clock/rockchip,rk3188.h +++ b/include/dt-bindings/clock/rockchip,rk3188.h @@ -23,6 +23,7 @@ #define CLKOPS_RATE_MAC_REF 10 #define CLKOPS_RATE_CORE 11 #define CLKOPS_RATE_CORE_PERI 12 +#define CLKOPS_RATE_DDR 13 #define CLKOPS_TABLE_END (~0)