From: Heiko Stübner Date: Tue, 1 Dec 2015 21:31:56 +0000 (+0100) Subject: clk: rockchip: fix rk3368 cpuclk divider offsets X-Git-Tag: firefly_0821_release~3561 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f96cb05dcd77f778e3b6ead9a30765540c4265ac;p=firefly-linux-kernel-4.4.55.git clk: rockchip: fix rk3368 cpuclk divider offsets Due to a copy-paste error the the rk3368 cpuclk settings were acessing rk3288-specific register offsets. This never caused problems till now, as cpu frequency scaling in't used currently at all. Change-Id: I525cbf5136f5986fc76e3d7bd090e51547dc2bf7 Reported-by: Xing Zheng Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 096a74f97c53..c3b84140483c 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -184,13 +184,13 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = { #define RK3368_CLKSEL0(_offs, _aclkm) \ { \ - .reg = RK3288_CLKSEL_CON(0 + _offs), \ + .reg = RK3368_CLKSEL_CON(0 + _offs), \ .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \ RK3368_DIV_ACLKM_SHIFT), \ } #define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \ { \ - .reg = RK3288_CLKSEL_CON(1 + _offs), \ + .reg = RK3368_CLKSEL_CON(1 + _offs), \ .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \ RK3368_DIV_ATCLK_SHIFT) | \ HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \