From: Benoit Goby <benoit@android.com>
Date: Tue, 3 Aug 2010 03:18:11 +0000 (-0700)
Subject: [ARM] tegra: clock: Add pll_u to common clock init table
X-Git-Tag: firefly_0821_release~9833^2~296
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=f9f01aa3c63e0d4d1792ca9a98a3eb7d0b9f43e1;p=firefly-linux-kernel-4.4.55.git

[ARM] tegra: clock: Add pll_u to common clock init table

Change-Id: I8cdef0406b6fe04551584ae0bae9534b4aec93f6
Signed-off-by: Benoit Goby <benoit@android.com>
---

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f0ba3b439255..d834347d21b7 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -45,6 +45,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 	{ "sclk",	"pll_p_out4",	108000000,	true },
 	{ "hclk",	"sclk",		108000000,	true },
 	{ "pclk",	"hclk",		54000000,	true },
+	{ "pll_u",	"clk_m",	480000000,	false },
 	{ NULL,		NULL,		0,		0},
 };