From: Nadav Rotem Date: Mon, 4 Jun 2012 11:27:21 +0000 (+0000) Subject: Remove the "-promote-elements" flag. This flag is now enabled by default. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=fcb2c3cf5e8ee421fd3a5639cc4a33036e9a614e;p=oota-llvm.git Remove the "-promote-elements" flag. This flag is now enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157925 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index ab32a841780..27447b5df7b 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -1720,13 +1720,6 @@ private: const TargetData *TD; const TargetLoweringObjectFile &TLOF; - /// We are in the process of implementing a new TypeLegalization action - /// which is the promotion of vector elements. This feature is under - /// development. Until this feature is complete, it is only enabled using a - /// flag. We pass this flag using a member because of circular dep issues. - /// This member will be removed with the flag once we complete the transition. - bool mayPromoteElements; - /// PointerTy - The type to use for pointers, usually i32 or i64. /// MVT PointerTy; @@ -1930,9 +1923,8 @@ private: if (NumElts == 1) return LegalizeKind(TypeScalarizeVector, EltVT); - // If we allow the promotion of vector elements using a flag, - // then try to widen vector elements until a legal type is found. - if (mayPromoteElements && EltVT.isInteger()) { + // Try to widen vector elements until a legal type is found. + if (EltVT.isInteger()) { // Vectors with a number of elements that is not a power of two are always // widened, for example <3 x float> -> <4 x float>. if (!VT.isPow2VectorType()) { diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index a54b5b1a8d7..2020cc7f7b0 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -33,13 +33,6 @@ #include using namespace llvm; -/// We are in the process of implementing a new TypeLegalization action -/// - the promotion of vector elements. This feature is disabled by default -/// and only enabled using this flag. -static cl::opt -AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true), - cl::desc("Allow promotion of integer vector element types")); - /// InitLibcallNames - Set default libcall names. /// static void InitLibcallNames(const char **Names) { @@ -522,8 +515,7 @@ static void InitCmpLibcallCCs(ISD::CondCode *CCs) { /// NOTE: The constructor takes ownership of TLOF. TargetLowering::TargetLowering(const TargetMachine &tm, const TargetLoweringObjectFile *tlof) - : TM(tm), TD(TM.getTargetData()), TLOF(*tlof), - mayPromoteElements(AllowPromoteIntElem) { + : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { // All operations default to being supported. memset(OpActions, 0, sizeof(OpActions)); memset(LoadExtActions, 0, sizeof(LoadExtActions)); @@ -829,11 +821,8 @@ void TargetLowering::computeRegisterProperties() { unsigned NElts = VT.getVectorNumElements(); if (NElts != 1) { bool IsLegalWiderType = false; - // If we allow the promotion of vector elements using a flag, - // then return TypePromoteInteger on vector elements. // First try to promote the elements of integer vectors. If no legal // promotion was found, fallback to the widen-vector method. - if (mayPromoteElements) for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { EVT SVT = (MVT::SimpleValueType)nVT; // Promote vectors of integers to vectors with the same number diff --git a/test/CodeGen/ARM/opt-shuff-tstore.ll b/test/CodeGen/ARM/opt-shuff-tstore.ll index b4da5524289..df98e231ccf 100644 --- a/test/CodeGen/ARM/opt-shuff-tstore.ll +++ b/test/CodeGen/ARM/opt-shuff-tstore.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=cortex-a9 -mtriple=arm-linux-unknown -promote-elements -mattr=+neon < %s | FileCheck %s +; RUN: llc -mcpu=cortex-a9 -mtriple=arm-linux-unknown -mattr=+neon < %s | FileCheck %s ; CHECK: func_4_8 ; CHECK: vst1.32 diff --git a/test/CodeGen/X86/2011-09-18-sse2cmp.ll b/test/CodeGen/X86/2011-09-18-sse2cmp.ll index 844d674fc9e..a6f428fdacc 100644 --- a/test/CodeGen/X86/2011-09-18-sse2cmp.ll +++ b/test/CodeGen/X86/2011-09-18-sse2cmp.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=x86 -mcpu=yonah -promote-elements -mattr=+sse2,-sse41 | FileCheck %s +;RUN: llc < %s -march=x86 -mcpu=yonah -mattr=+sse2,-sse41 | FileCheck %s ;CHECK: @max ;CHECK: cmplepd diff --git a/test/CodeGen/X86/2011-09-21-setcc-bug.ll b/test/CodeGen/X86/2011-09-21-setcc-bug.ll index ed5649c6026..4daf6781495 100644 --- a/test/CodeGen/X86/2011-09-21-setcc-bug.ll +++ b/test/CodeGen/X86/2011-09-21-setcc-bug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mcpu=corei7 -promote-elements -mattr=+sse41 +; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+sse41 ; Make sure we are not crashing on this code. diff --git a/test/CodeGen/X86/2011-10-11-srl.ll b/test/CodeGen/X86/2011-10-11-srl.ll index cf9d36f1c48..6c6d340fd1a 100644 --- a/test/CodeGen/X86/2011-10-11-srl.ll +++ b/test/CodeGen/X86/2011-10-11-srl.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -promote-elements -mattr=-sse41 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=-sse41 target triple = "x86_64-unknown-linux-gnu" diff --git a/test/CodeGen/X86/4char-promote.ll b/test/CodeGen/X86/4char-promote.ll index 6d7bc0cc702..4f1a859fd43 100644 --- a/test/CodeGen/X86/4char-promote.ll +++ b/test/CodeGen/X86/4char-promote.ll @@ -1,11 +1,11 @@ ; A test for checking PR 9623 -; RUN: llc -march=x86-64 -mcpu=corei7 -promote-elements < %s | FileCheck %s +; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s target triple = "x86_64-apple-darwin" -; CHECK: pmulld -; CHECK: paddd -; CHECK-NOT: movdqa +; CHECK: pmulld +; CHECK: paddd +; CHECK-NOT: movdqa ; CHECK: ret define <4 x i8> @foo(<4 x i8> %x, <4 x i8> %y) { diff --git a/test/CodeGen/X86/avx-blend.ll b/test/CodeGen/X86/avx-blend.ll index 77294917339..188efe26d92 100644 --- a/test/CodeGen/X86/avx-blend.ll +++ b/test/CodeGen/X86/avx-blend.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -promote-elements -mattr=+avx | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s ; AVX128 tests: diff --git a/test/CodeGen/X86/avx-minmax.ll b/test/CodeGen/X86/avx-minmax.ll index 737fa6e4163..eff92510348 100644 --- a/test/CodeGen/X86/avx-minmax.ll +++ b/test/CodeGen/X86/avx-minmax.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+avx -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=UNSAFE %s +; RUN: llc < %s -march=x86-64 -mattr=+avx -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s ; UNSAFE: maxpd: ; UNSAFE: vmaxpd {{.+}}, %xmm diff --git a/test/CodeGen/X86/basic-promote-integers.ll b/test/CodeGen/X86/basic-promote-integers.ll index c80f2b03343..fce6b7f5565 100644 --- a/test/CodeGen/X86/basic-promote-integers.ll +++ b/test/CodeGen/X86/basic-promote-integers.ll @@ -1,7 +1,7 @@ ; Test that vectors are scalarized/lowered correctly ; (with both legalization methods). -; RUN: llc -march=x86 -promote-elements < %s -; RUN: llc -march=x86 < %s +; RUN: llc -march=x86 < %s +; RUN: llc -march=x86 < %s ; A simple test to check copyToParts and copyFromParts. diff --git a/test/CodeGen/X86/blend-msb.ll b/test/CodeGen/X86/blend-msb.ll index 3a10c70ada8..11f811f8cf6 100644 --- a/test/CodeGen/X86/blend-msb.ll +++ b/test/CodeGen/X86/blend-msb.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -promote-elements -mattr=+sse41 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse41 | FileCheck %s ; In this test we check that sign-extend of the mask bit is performed by diff --git a/test/CodeGen/X86/mem-promote-integers.ll b/test/CodeGen/X86/mem-promote-integers.ll index 80103d10388..0015df0c1fa 100644 --- a/test/CodeGen/X86/mem-promote-integers.ll +++ b/test/CodeGen/X86/mem-promote-integers.ll @@ -1,8 +1,8 @@ ; Test the basic functionality of integer element promotions of different types. ; This tests checks passing of arguments, loading and storing to memory and ; basic arithmetic. -; RUN: llc -march=x86 -promote-elements < %s -; RUN: llc -march=x86-64 -promote-elements < %s +; RUN: llc -march=x86 < %s +; RUN: llc -march=x86-64 < %s define <1 x i8> @test_1xi8(<1 x i8> %x, <1 x i8>* %b) { %bb = load <1 x i8>* %b diff --git a/test/CodeGen/X86/opt-shuff-tstore.ll b/test/CodeGen/X86/opt-shuff-tstore.ll index fc24913be52..3e720844c43 100644 --- a/test/CodeGen/X86/opt-shuff-tstore.ll +++ b/test/CodeGen/X86/opt-shuff-tstore.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux < %s -promote-elements -mattr=+sse2,+sse41 | FileCheck %s +; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux < %s -mattr=+sse2,+sse41 | FileCheck %s ; CHECK: func_4_8 ; A single memory write diff --git a/test/CodeGen/X86/promote-trunc.ll b/test/CodeGen/X86/promote-trunc.ll index 4211d82268d..40a58b07392 100644 --- a/test/CodeGen/X86/promote-trunc.ll +++ b/test/CodeGen/X86/promote-trunc.ll @@ -1,4 +1,4 @@ -; RUN: llc -promote-elements < %s -march=x86-64 +; RUN: llc < %s -march=x86-64 define<4 x i8> @func_8_64() { %F = load <4 x i64>* undef diff --git a/test/CodeGen/X86/sse-minmax.ll b/test/CodeGen/X86/sse-minmax.ll index ee7aa064260..4405f684512 100644 --- a/test/CodeGen/X86/sse-minmax.ll +++ b/test/CodeGen/X86/sse-minmax.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -promote-elements | FileCheck %s -; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=UNSAFE %s -; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=FINITE %s +; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s +; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s ; Some of these patterns can be matched as SSE min or max. Some of ; then can be matched provided that the operands are swapped. diff --git a/test/CodeGen/X86/sse41-blend.ll b/test/CodeGen/X86/sse41-blend.ll index 1a1017d2c17..a2a0debf9e9 100644 --- a/test/CodeGen/X86/sse41-blend.ll +++ b/test/CodeGen/X86/sse41-blend.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -promote-elements -mattr=+sse41 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse41 | FileCheck %s ;CHECK: vsel_float ;CHECK: blendvps diff --git a/test/CodeGen/X86/trunc-ext-ld-st.ll b/test/CodeGen/X86/trunc-ext-ld-st.ll index 57d6e97767b..9877d7be169 100644 --- a/test/CodeGen/X86/trunc-ext-ld-st.ll +++ b/test/CodeGen/X86/trunc-ext-ld-st.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mcpu=corei7 -promote-elements -mattr=+sse41 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+sse41 | FileCheck %s ;CHECK: load_2_i8 ; A single 16-bit load