From: Evgeniy Stepanov Date: Thu, 24 Apr 2014 09:56:15 +0000 (+0000) Subject: [asan] Fix instrumentation of x86 intel syntax inline assembly. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=fd46b84dddfdb736b7d3c70d17ee934b6cbb39f8;p=oota-llvm.git [asan] Fix instrumentation of x86 intel syntax inline assembly. Patch by Yuri Gorshenin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207092 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp index 51c378976c8..4829165892e 100644 --- a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp +++ b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp @@ -82,60 +82,60 @@ void X86AddressSanitizer::InstrumentMOV( MCContext &Ctx, MCStreamer &Out) { // Access size in bytes. unsigned AccessSize = 0; - unsigned long OpIx = Operands.size(); + + // FIXME: use MCInstrDesc to get proper value of IsWrite. + bool IsWrite = false; switch (Inst.getOpcode()) { case X86::MOV8mi: case X86::MOV8mr: AccessSize = 1; - OpIx = 2; + IsWrite = true; break; case X86::MOV8rm: AccessSize = 1; - OpIx = 1; break; case X86::MOV16mi: case X86::MOV16mr: AccessSize = 2; - OpIx = 2; + IsWrite = true; break; case X86::MOV16rm: AccessSize = 2; - OpIx = 1; break; case X86::MOV32mi: case X86::MOV32mr: AccessSize = 4; - OpIx = 2; + IsWrite = true; break; case X86::MOV32rm: AccessSize = 4; - OpIx = 1; break; case X86::MOV64mi32: case X86::MOV64mr: AccessSize = 8; - OpIx = 2; + IsWrite = true; break; case X86::MOV64rm: AccessSize = 8; - OpIx = 1; break; case X86::MOVAPDmr: case X86::MOVAPSmr: AccessSize = 16; - OpIx = 2; + IsWrite = true; break; case X86::MOVAPDrm: case X86::MOVAPSrm: AccessSize = 16; - OpIx = 1; break; - } - if (OpIx >= Operands.size()) + default: return; + } - const bool IsWrite = (OpIx != 1); - InstrumentMemOperand(Operands[OpIx], AccessSize, IsWrite, Ctx, Out); + for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) { + MCParsedAsmOperand *Op = Operands[Ix]; + if (Op && Op->isMem()) + InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out); + } } class X86AddressSanitizer32 : public X86AddressSanitizer { diff --git a/test/Instrumentation/AddressSanitizer/X86/asm_swap_intel.s b/test/Instrumentation/AddressSanitizer/X86/asm_swap_intel.s new file mode 100644 index 00000000000..4144bf5e565 --- /dev/null +++ b/test/Instrumentation/AddressSanitizer/X86/asm_swap_intel.s @@ -0,0 +1,71 @@ +# RUN: llvm-mc %s -x86-asm-syntax=intel -triple=x86_64-unknown-linux-gnu -asm-instrumentation=address | FileCheck %s + + .text + .globl swap + .align 16, 0x90 + .type swap,@function +# CHECK-LABEL: swap: +# +# CHECK: subq $128, %rsp +# CHECK-NEXT: pushq %rdi +# CHECK-NEXT: leaq (%rcx), %rdi +# CHECK-NEXT: callq __sanitizer_sanitize_load8@PLT +# CHECK-NEXT: popq %rdi +# CHECK-NEXT: addq $128, %rsp +# +# CHECK-NEXT: movq (%rcx), %rax +# +# CHECK-NEXT: subq $128, %rsp +# CHECK-NEXT: pushq %rdi +# CHECK-NEXT: leaq (%rdx), %rdi +# CHECK-NEXT: callq __sanitizer_sanitize_load8@PLT +# CHECK-NEXT: popq %rdi +# CHECK-NEXT: addq $128, %rsp +# +# CHECK-NEXT: movq (%rdx), %rbx +# +# CHECK: subq $128, %rsp +# CHECK-NEXT: pushq %rdi +# CHECK-NEXT: leaq (%rcx), %rdi +# CHECK-NEXT: callq __sanitizer_sanitize_store8@PLT +# CHECK-NEXT: popq %rdi +# CHECK-NEXT: addq $128, %rsp +# +# CHECK-NEXT: movq %rbx, (%rcx) +# +# CHECK-NEXT: subq $128, %rsp +# CHECK-NEXT: pushq %rdi +# CHECK-NEXT: leaq (%rdx), %rdi +# CHECK-NEXT: callq __sanitizer_sanitize_store8@PLT +# CHECK-NEXT: popq %rdi +# CHECK-NEXT: addq $128, %rsp +# +# CHECK-NEXT: movq %rax, (%rdx) +swap: # @swap + .cfi_startproc +# BB#0: + push rbx +.Ltmp0: + .cfi_def_cfa_offset 16 +.Ltmp1: + .cfi_offset rbx, -16 + mov rcx, rdi + mov rdx, rsi + #APP + + + mov rax, qword ptr [rcx] + mov rbx, qword ptr [rdx] + mov qword ptr [rcx], rbx + mov qword ptr [rdx], rax + + #NO_APP + pop rbx + ret +.Ltmp2: + .size swap, .Ltmp2-swap + .cfi_endproc + + + .ident "clang version 3.5.0 " + .section ".note.GNU-stack","",@progbits