From: Iliyan Malchev <malchev@google.com>
Date: Mon, 4 Oct 2010 22:11:37 +0000 (-0700)
Subject: [ARM] tegra: dma: fix a typo
X-Git-Tag: firefly_0821_release~9833^2~175
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=fd7a27ca4b8a96b96b5f5faa98955c760f80d801;p=firefly-linux-kernel-4.4.55.git

[ARM] tegra: dma: fix a typo

Signed-off-by: Iliyan Malchev <malchev@google.com>
---

diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index c2bb582b96cd..87309818d254 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -242,7 +242,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
 	if (status & STA_BUSY)
 		req->bytes_transferred -= to_transfer;
 
-	/* In continous transfer mode, DMA only tracks the count of the
+	/* In continuous transfer mode, DMA only tracks the count of the
 	 * half DMA buffer. So, if the DMA already finished half the DMA
 	 * then add the half buffer to the completed count.
 	 *
@@ -250,7 +250,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
 	 *	dequue happens at the same time as the DMA just moved to
 	 *	the new buffer and SW didn't yet received the interrupt?
 	 */
-	if (ch->mode & TEGRA_DMA_MODE_CONTINOUS)
+	if (ch->mode & TEGRA_DMA_MODE_CONTINUOUS)
 		if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
 			req->bytes_transferred += req_transfer_count;
 
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 39011bd9a925..81e62782bac7 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -58,7 +58,7 @@ struct tegra_dma_channel;
 
 enum tegra_dma_mode {
 	TEGRA_DMA_SHARED = 1,
-	TEGRA_DMA_MODE_CONTINOUS = 2,
+	TEGRA_DMA_MODE_CONTINUOUS = 2,
 	TEGRA_DMA_MODE_ONESHOT = 4,
 };
 
@@ -92,11 +92,11 @@ struct tegra_dma_req {
 	/*  This is a called from the DMA ISR context when the DMA is still in
 	 *  progress and is actively filling same buffer.
 	 *
-	 *  In case of continous mode receive, this threshold is 1/2 the buffer
+	 *  In case of continuous mode receive, this threshold is 1/2 the buffer
 	 *  size. In other cases, this will not even be called as there is no
 	 *  hardware support for it.
 	 *
-	 * In the case of continous mode receive, if there is next req already
+	 * In the case of continuous mode receive, if there is next req already
 	 * queued, DMA programs the HW to use that req when this req is
 	 * completed. If there is no "next req" queued, then DMA ISR doesn't do
 	 * anything before calling this callback.