From: Okash Khawaja Date: Mon, 11 May 2015 11:58:31 +0000 (+0100) Subject: adm8211: fixed the possible pci cache line sizes inside switch-case X-Git-Tag: firefly_0821_release~176^2~1587^2~139^2~38 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=fe0a483ecf4458e94ebe58d7fedc6d56e21eed56;p=firefly-linux-kernel-4.4.55.git adm8211: fixed the possible pci cache line sizes inside switch-case The PCI cache line size value was being compared against decimal values prefixed with 0x. Fixed the literals to use the correct hex values. This has not been tested due to lack of hardware. However, the value in `cline` is PCI cache line size, which is the CPU's cache line size. It is less likely for cache line sizes to be 22 or 50, and more likely for them to be 16 or 32. Also, as far as I understand, cache line size is used for things like aligning DMA requests with CPU cache line, which improve performance but wouldn't break anything if the value doesn't match. In this case, we will fall through to the default case which leaves `reg` unchanged. Signed-off-by: Okash Khawaja Signed-off-by: Kalle Valo --- diff --git a/drivers/net/wireless/adm8211.c b/drivers/net/wireless/adm8211.c index faf277e0a646..8c283fcd843d 100644 --- a/drivers/net/wireless/adm8211.c +++ b/drivers/net/wireless/adm8211.c @@ -1101,10 +1101,10 @@ static void adm8211_hw_init(struct ieee80211_hw *dev) case 0x8: reg |= (0x1 << 14); break; - case 0x16: + case 0x10: reg |= (0x2 << 14); break; - case 0x32: + case 0x20: reg |= (0x3 << 14); break; default: