From: Caesar Wang Date: Thu, 30 Jun 2016 11:11:08 +0000 (+0800) Subject: FROMLIST: arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs X-Git-Tag: firefly_0821_release~2058 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=ff7e1390761dba7c224eb2c7da0b01a4a064904b;p=firefly-linux-kernel-4.4.55.git FROMLIST: arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs Add the interrupts cells value for 4, and the 4th cell is zero. Due to the doc[0] said:" the system requires describing PPI affinity, then the value must be at least 4" The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For interrupt types other than PPI or PPIs that are not partitionned, this cell must be zero. See the "ppi-partitions" node description below. [0]: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Change-Id: I80d459b746aea40027a7eacfcc7aa764a57fdc9f Acked-by: Mark Rutland Signed-off-by: Caesar Wang (am https://patchwork.kernel.org/patch/9215659/) (Note: fixes some no sync upstream node) --- diff --git a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi index eefcbfa7f66e..a5911c8ed015 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi @@ -166,8 +166,8 @@ rockchip,grf = <&grf>; iommu_enabled = <1>; reg = <0x0 0xff650000 0x0 0x800>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "irq_dec", "irq_enc"; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; clock-names = "aclk_vcodec", "hclk_vcodec"; @@ -182,7 +182,7 @@ dbgname = "vpu"; compatible = "rockchip,vpu_mmu"; reg = <0x0 0xff650800 0x0 0x40>; - interrupts = ; + interrupts = ; interrupt-names = "vpu_mmu"; }; @@ -191,7 +191,7 @@ rockchip,grf = <&grf>; iommu_enabled = <1>; reg = <0x0 0xff660000 0x0 0x400>; - interrupts = ; + interrupts = ; interrupt-names = "irq_dec"; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>; clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core"; @@ -207,7 +207,7 @@ compatible = "rockchip,vdec_mmu"; reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; - interrupts = ; + interrupts = ; interrupt-names = "vdec_mmu"; }; @@ -215,7 +215,7 @@ compatible = "rockchip,iep"; iommu_enabled = <1>; reg = <0x0 0xff670000 0x0 0x800>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk_iep", "hclk_iep"; power-domains = <&power RK3399_PD_IEP>; @@ -226,7 +226,7 @@ dbgname = "iep"; compatible = "rockchip,iep_mmu"; reg = <0x0 0xff670800 0x0 0x40>; - interrupts = ; + interrupts = ; interrupt-names = "iep_mmu"; }; @@ -234,7 +234,7 @@ compatible = "rockchip,rga2"; dev_mode = <1>; reg = <0x0 0xff680000 0x0 0x1000>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; clock-names = "aclk_rga", "hclk_rga", "clk_rga"; power-domains = <&power RK3399_PD_RGA>; @@ -259,7 +259,7 @@ compatible = "rockchip,rk3399-lcdc"; rockchip,prop = ; reg = <0x0 0xff900000 0x0 0x3efc>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; @@ -275,7 +275,7 @@ dbgname = "vop"; compatible = "rockchip,vopb_mmu"; reg = <0x0 0xff903f00 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "vopb_mmu"; }; @@ -284,7 +284,7 @@ compatible = "rockchip,rk3399-lcdc"; rockchip,prop = ; reg = <0x0 0xff8f0000 0x0 0x3efc>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; @@ -300,14 +300,14 @@ dbgname = "vop"; compatible = "rockchip,vopl_mmu"; reg = <0x0 0xff8f3f00 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "vopl_mmu"; }; isp0: isp@ff910000 { compatible = "rockchip,rk3399-isp", "rockchip,isp"; reg = <0x0 0xff910000 0x0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>, @@ -346,14 +346,14 @@ compatible = "rockchip,isp0_mmu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "isp0_mmu"; }; isp1: isp@ff920000 { compatible = "rockchip,rk3399-isp", "rockchip,isp"; reg = <0x0 0xff920000 0x0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>, @@ -394,7 +394,7 @@ compatible = "rockchip,isp1_mmu"; reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "isp1_mmu"; }; @@ -402,8 +402,8 @@ status = "disabled"; compatible = "rockchip,rk3399-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; - interrupts = , - ; + interrupts = , + ; clocks = <&cru PCLK_HDMI_CTRL>, <&cru HCLK_HDCP>, <&cru SCLK_HDMI_CEC>, @@ -428,7 +428,7 @@ rockchip,prop = <0>; rockchip,grf = <&grf>; reg = <0x0 0xff960000 0x0 0x8000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>; clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg"; power-domains = <&power RK3399_PD_VIO>; @@ -440,7 +440,7 @@ rockchip,prop = <1>; rockchip,grf = <&grf>; reg = <0x0 0xff968000 0x0 0x8000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>; clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg"; power-domains = <&power RK3399_PD_VIO>; @@ -451,7 +451,7 @@ compatible = "rockchip,rk3399-edp-fb"; reg = <0x0 0xff970000 0x0 0x8000>; rockchip,grf = <&grf>; - interrupts = ; + interrupts = ; clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "clk_edp", "pclk_edp"; resets = <&cru SRST_P_EDP_CTRL>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-box-808-android.dts b/arch/arm64/boot/dts/rockchip/rk3399-box-808-android.dts index 51f42e3e3b32..bca58e9e06f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-box-808-android.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-box-808-android.dts @@ -615,7 +615,7 @@ &pwm3 { status = "disabled"; - interrupts = ; + interrupts = ; compatible = "rockchip,remotectl-pwm"; remote_pwm_id = <3>; handle_cpu_id = <0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-box.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-box.dtsi index d091fd0a50cf..fb0c784dbb07 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-box.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-box.dtsi @@ -785,7 +785,7 @@ &pwm3 { status = "okay"; - interrupts = ; + interrupts = ; compatible = "rockchip,remotectl-pwm"; remote_pwm_id = <3>; handle_cpu_id = <0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a8cc5bd22bdc..7ee53786ce00 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -254,15 +254,15 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; arm-pmu { compatible = "arm,armv8-pmuv3"; - interrupts = ; + interrupts = ; }; xin24m: xin24m { @@ -281,8 +281,8 @@ dmac_bus: dma-controller@ff6d0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = , - ; + interrupts = , + ; #dma-cells = <1>; clocks = <&cru ACLK_DMAC0_PERILP>; clock-names = "apb_pclk"; @@ -292,8 +292,8 @@ dmac_peri: dma-controller@ff6e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = , - ; + interrupts = , + ; #dma-cells = <1>; clocks = <&cru ACLK_DMAC1_PERILP>; clock-names = "apb_pclk"; @@ -305,7 +305,7 @@ compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>; rockchip,grf = <&grf>; - interrupts = ; + interrupts = ; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, @@ -333,7 +333,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = ; + interrupts = ; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; @@ -346,7 +346,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = ; + interrupts = ; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; @@ -358,7 +358,7 @@ sdhci: sdhci@fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; clock-names = "clk_xin", "clk_ahb"; assigned-clocks = <&cru SCLK_EMMC>; @@ -372,7 +372,7 @@ usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = ; + interrupts = ; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&cru SCLK_USBPHY0_480M_SRC>; clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; @@ -384,7 +384,7 @@ usb_host0_ohci: usb@fe3a0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = ; + interrupts = ; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&cru SCLK_USBPHY0_480M_SRC>; clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; @@ -396,7 +396,7 @@ usb_host1_ehci: usb@fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = ; + interrupts = ; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, <&cru SCLK_USBPHY1_480M_SRC>; clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; @@ -408,7 +408,7 @@ usb_host1_ohci: usb@fe3e0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = ; + interrupts = ; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, <&cru SCLK_USBPHY1_480M_SRC>; clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; @@ -432,7 +432,7 @@ usbdrd_dwc3_0: dwc3@fe800000 { compatible = "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; - interrupts = ; + interrupts = ; dr_mode = "otg"; snps,dis_enblslpm_quirk; snps,phyif_utmi_16_bits; @@ -458,7 +458,7 @@ usbdrd_dwc3_1: dwc3@fe900000 { compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; - interrupts = ; + interrupts = ; dr_mode = "otg"; snps,dis_enblslpm_quirk; snps,phyif_utmi_16_bits; @@ -471,7 +471,7 @@ gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; + #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -482,7 +482,7 @@ <0x0 0xfff00000 0 0x10000>, /* GICC */ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = ; + interrupts = ; its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; @@ -493,7 +493,7 @@ saradc: saradc@ff100000 { compatible = "rockchip,rk3399-saradc"; reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; + interrupts = ; #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; @@ -505,7 +505,7 @@ reg = <0x0 0xff3c0000 0x0 0x1000>; clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; #address-cells = <1>; @@ -518,7 +518,7 @@ reg = <0x0 0xff110000 0x0 0x1000>; clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c1_xfer>; #address-cells = <1>; @@ -531,7 +531,7 @@ reg = <0x0 0xff120000 0x0 0x1000>; clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; #address-cells = <1>; @@ -544,7 +544,7 @@ reg = <0x0 0xff130000 0x0 0x1000>; clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c3_xfer>; #address-cells = <1>; @@ -557,7 +557,7 @@ reg = <0x0 0xff140000 0x0 0x1000>; clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c5_xfer>; #address-cells = <1>; @@ -570,7 +570,7 @@ reg = <0x0 0xff150000 0x0 0x1000>; clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c6_xfer>; #address-cells = <1>; @@ -583,7 +583,7 @@ reg = <0x0 0xff160000 0x0 0x1000>; clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; #address-cells = <1>; @@ -596,7 +596,7 @@ reg = <0x0 0xff180000 0x0 0x100>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -609,7 +609,7 @@ reg = <0x0 0xff190000 0x0 0x100>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -622,7 +622,7 @@ reg = <0x0 0xff1a0000 0x0 0x100>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -635,7 +635,7 @@ reg = <0x0 0xff1b0000 0x0 0x100>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -648,7 +648,7 @@ reg = <0x0 0xff1c0000 0x0 0x1000>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -661,7 +661,7 @@ reg = <0x0 0xff1d0000 0x0 0x1000>; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -674,7 +674,7 @@ reg = <0x0 0xff1e0000 0x0 0x1000>; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -687,7 +687,7 @@ reg = <0x0 0xff1f0000 0x0 0x1000>; clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -700,7 +700,7 @@ reg = <0x0 0xff200000 0x0 0x1000>; clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; #address-cells = <1>; @@ -767,7 +767,7 @@ tsadc: tsadc@ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; - interrupts = ; + interrupts = ; rockchip,grf = <&grf>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; @@ -980,7 +980,7 @@ reg = <0x0 0xff350000 0x0 0x1000>; clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; clock-names = "spiclk", "apb_pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; #address-cells = <1>; @@ -993,7 +993,7 @@ reg = <0x0 0xff370000 0x0 0x100>; clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; clock-names = "baudclk", "apb_pclk"; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -1006,7 +1006,7 @@ reg = <0x0 0xff3d0000 0x0 0x1000>; clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; #address-cells = <1>; @@ -1019,7 +1019,7 @@ reg = <0x0 0xff3e0000 0x0 0x1000>; clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; clock-names = "i2c", "pclk"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c8_xfer>; #address-cells = <1>; @@ -1036,9 +1036,9 @@ clock-names = "aclk_pcie", "aclk_perf_pcie", "hclk_pcie", "clk_pciephy_ref"; bus-range = <0x0 0x1>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client"; ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >; @@ -1116,7 +1116,7 @@ rga: rga@ff680000 { compatible = "rockchip,rk3399-rga"; reg = <0x0 0xff680000 0x0 0x10000>; - interrupts = ; + interrupts = ; interrupt-names = "rga"; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; clock-names = "aclk", "hclk", "sclk"; @@ -1180,9 +1180,9 @@ u2phy0_otg: otg-port { #phy-cells = <0>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "otg-bvalid", "otg-id", "linestate"; status = "disabled"; @@ -1190,7 +1190,7 @@ u2phy0_host: host-port { #phy-cells = <0>; - interrupts = ; + interrupts = ; interrupt-names = "linestate"; status = "disabled"; }; @@ -1207,7 +1207,7 @@ u2phy1_host: host-port { #phy-cells = <0>; - interrupts = ; + interrupts = ; interrupt-names = "linestate"; status = "disabled"; }; @@ -1258,13 +1258,13 @@ compatible = "snps,dw-wdt"; reg = <0x0 0xff840000 0x0 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = ; + interrupts = ; }; rktimer: rktimer@ff850000 { compatible = "rockchip,rk3399-timer"; reg = <0x0 0xff850000 0x0 0x1000>; - interrupts = ; + interrupts = ; clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; clock-names = "pclk", "timer"; }; @@ -1272,7 +1272,7 @@ spdif: spdif@ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = ; + interrupts = ; dmas = <&dmac_bus 7>; dma-names = "tx"; clock-names = "mclk", "hclk"; @@ -1286,7 +1286,7 @@ compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; rockchip,grf = <&grf>; - interrupts = ; + interrupts = ; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -1299,7 +1299,7 @@ i2s1: i2s@ff890000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = ; + interrupts = ; dmas = <&dmac_bus 2>, <&dmac_bus 3>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -1312,7 +1312,7 @@ i2s2: i2s@ff8a0000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = ; + interrupts = ; dmas = <&dmac_bus 4>, <&dmac_bus 5>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -1328,9 +1328,9 @@ reg = <0x0 0xff9a0000 0x0 0x10000>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "GPU", "JOB", "MMU"; clocks = <&cru ACLK_GPU>; @@ -1374,7 +1374,7 @@ vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit"; reg = <0x0 0xff8f0000 0x0 0x3efc>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; @@ -1407,7 +1407,7 @@ vopl_mmu: iommu@ff8f3f00 { compatible = "rockchip,iommu"; reg = <0x0 0xff8f3f00 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "vopl_mmu"; #iommu-cells = <0>; status = "disabled"; @@ -1416,7 +1416,7 @@ vopb: vop@ff900000 { compatible = "rockchip,rk3399-vop-big"; reg = <0x0 0xff900000 0x0 0x3efc>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; @@ -1449,7 +1449,7 @@ vopb_mmu: iommu@ff903f00 { compatible = "rockchip,iommu"; reg = <0x0 0xff903f00 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "vopb_mmu"; #iommu-cells = <0>; status = "disabled"; @@ -1461,7 +1461,7 @@ reg-io-width = <4>; rockchip,grf = <&grf>; power-domains = <&power RK3399_PD_HDCP>; - interrupts = ; + interrupts = ; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>; clock-names = "iahb", "isfr", "vpll", "grf"; status = "disabled"; @@ -1485,7 +1485,7 @@ mipi_dsi: mipi@ff960000 { compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_DPHY_TX0_CFG>; clock-names = "ref", "pclk", "phy_cfg"; @@ -1519,7 +1519,7 @@ edp: edp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>; - interrupts = ; + interrupts = ; clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; resets = <&cru SRST_P_EDP_CTRL>; @@ -1569,7 +1569,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -1582,7 +1582,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -1595,7 +1595,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -1608,7 +1608,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>; @@ -1621,7 +1621,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <0x2>;