From: Daniel Vetter Date: Sat, 27 Oct 2012 13:50:28 +0000 (+0200) Subject: drm/i915: clarify why we need to enable fdi plls so early X-Git-Tag: firefly_0821_release~3680^2~1383^2~193^2~102 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=fff367c752f5fb998882c7bc0a213ab1e53857db;p=firefly-linux-kernel-4.4.55.git drm/i915: clarify why we need to enable fdi plls so early For reference, see "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence", step 4 of the enabling sequence: a. "Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency b. "Switch from Rawclk to PCDclk in FDI Receiver c. "Enable CPU FDI Transmitter PLL, wait for warmup" Cc: Paulo Zanoni Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 54b1794c3403..612b4105b758 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3227,6 +3227,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) is_pch_port = ironlake_crtc_driving_pch(crtc); if (is_pch_port) { + /* Note: FDI PLL enabling _must_ be done before we enable the + * cpu pipes, hence this is separate from all the other fdi/pch + * enabling. */ ironlake_fdi_pll_enable(intel_crtc); } else { assert_fdi_tx_disabled(dev_priv, pipe);