[another test commit, just to tickle the selfhost buildbots; I'll back out in a few...
[oota-llvm.git] / include / llvm / Target /
2010-07-02 Jakob Stoklund OlesenAdd a new target independent COPY instruction and code...
2010-07-02 Jakob Stoklund OlesenClean up TargetOpcodes.h a bit, and limit the number...
2010-06-29 Bill WendlingRevert r107205 and r107207.
2010-06-29 Bill WendlingIntroducing the "linker_weak" linkage type. This will...
2010-06-29 Rafael EspindolaAdd a VT argument to getMinimalPhysRegClass and replace...
2010-06-25 Evan ChengChange if-conversion block size limit checks to add...
2010-06-25 Dale JohannesenThe hasMemory argument is irrelevant to how the argument
2010-06-24 Bob WilsonEdit and clarify comments for TargetInstrInfo methods:
2010-06-24 Dan GohmanReapply r106634, now that the bug it exposed is fixed.
2010-06-23 Daniel DunbarRevert r106263, "Fold the ShrinkDemandedOps pass into...
2010-06-23 Jim GrosbachSome targets don't require the fencing MEMBARRIER instr...
2010-06-23 Jim Grosbachremove trailing whitespace
2010-06-22 Evan ChengTail merging pass shall not break up IT blocks. rdar...
2010-06-21 Eric ChristopherRemove isTwoAddress from llvm.
2010-06-18 Evan ChengAllow ARM if-converter to be run after post allocation...
2010-06-18 Dan GohmanStart TargetRegisterClass indices at 0 instead of 1...
2010-06-18 Dan GohmanFold the ShrinkDemandedOps pass into the regular DAGCom...
2010-06-17 Stuart HastingsAdd a DebugLoc parameter to TargetInstrInfo::InsertBran...
2010-06-14 Bob WilsonFix a comment typo.
2010-06-12 Chris Lattnerdeclare a class with 'class' instead of struct to avoid...
2010-06-12 Evan ChengAllow target to provide its own hazard recognizer to...
2010-06-09 Evan ChengAllow target to place 2-address pass inserted copies...
2010-06-09 Bill Wendling- Fix description of SUBREG_TO_REG. It's not going...
2010-06-08 Bruno Cardoso LopesReapply r105521, this time appending "LLU" to 64 bit
2010-06-05 Chris Lattnerrevert r105521, which is breaking the buildbots with...
2010-06-05 Bruno Cardoso LopesInitial AVX support for some instructions. No patterns...
2010-06-02 Jakob Stoklund OlesenSlightly change the meaning of the reMaterialize target...
2010-06-02 Bob WilsonRename canCombinedSubRegIndex method to something more...
2010-06-02 Rafael EspindolaRemove uses of getCalleeSavedRegClasses from outside the
2010-05-28 Jakob Stoklund OlesenAdd a TargetRegisterInfo::composeSubRegIndices hook...
2010-05-26 Daniel DunbarMC: Add TargetMachine support for setting the value...
2010-05-26 Daniel DunbarMC: Change RelaxInstruction to only take the input...
2010-05-26 Daniel DunbarMC: Simplify MayNeedRelaxation to not provide the fixup...
2010-05-26 Jakob Stoklund OlesenReplace the SubRegSet tablegen class with a less error...
2010-05-26 Daniel DunbarMC: Eliminate MCAsmFixup, replace with MCFixup.
2010-05-26 Jakob Stoklund OlesenRevert "Replace the SubRegSet tablegen class with a...
2010-05-26 Jakob Stoklund OlesenReplace the SubRegSet tablegen class with a less error...
2010-05-25 Jakob Stoklund OlesenDrop the SuperregHashTable. It is essentially the same...
2010-05-25 Jakob Stoklund OlesenPrint symbolic SubRegIndex names on machine operands.
2010-05-25 Jakob Stoklund OlesenRemove NumberHack entirely.
2010-05-24 Jakob Stoklund OlesenSwitch SubRegSet to using symbolic SubRegIndices
2010-05-24 Jakob Stoklund OlesenReplace the tablegen RegisterClass field SubRegClassLis...
2010-05-24 Jakob Stoklund OlesenAdd the SubRegIndex TableGen class.
2010-05-22 Daniel Dunbartblgen/AsmMatcher: Change AsmOperandClass to allow...
2010-05-22 Evan ChengImplement @llvm.returnaddress. rdar://8015977.
2010-05-22 Eric ChristopherAdd a new section and accessor for TLS data.
2010-05-21 Matt FlemingCurrently, createMachOStreamer() is invoked directly...
2010-05-20 Evan ChengAllow targets more controls on what nodes are scheduled...
2010-05-20 Daniel Dunbartblgen/Target: Add a isAsmParserOnly bit, and teach...
2010-05-20 Evan ChengAdd a hybrid bottom up scheduler that reduce register...
2010-05-19 Evan ChengCode refactoring: pull SchedPreference enum from Target...
2010-05-15 Evan ChengAllow TargetLowering::getRegClassFor() to be called...
2010-05-14 Evan ChengTeach two-address pass to do some coalescing while...
2010-05-14 Evan ChengGet rid of the bit twiddling to read / set OpActions...
2010-05-13 Evan ChengEliminate use of magic numbers to access OpActions...
2010-05-13 Evan ChengFix up LoadExtActions, TruncStoreActions, and IndexedMo...
2010-05-13 Evan Cheng80 col violation.
2010-05-12 Daniel DunbarMC/Mach-O/x86_64: Add a new hook for checking whether...
2010-05-11 Dan GohmanRemove the "WantsWholeFile" concept, as it's no longer...
2010-05-11 Dan GohmanTrim #includes and forward declarations.
2010-05-11 Dan GohmanFix a comment.
2010-05-11 Dan GohmanImplement a bunch more TargetSelectionDAGInfo infrastru...
2010-05-11 Dan GohmanRemove the TargetLowering::getSubtarget() virtual funct...
2010-05-11 Bill WendlingThe getDefaultSubtargetFeatures method of SubtargetFeat...
2010-05-06 Dan GohmanAdd a DebugLoc argument to TargetInstrInfo::copyRegToRe...
2010-05-06 Evan ChengAdd argument TargetRegisterInfo to loadRegFromStackSlot...
2010-05-04 Daniel DunbarMC/Matcher: Add support for over-riding the default...
2010-05-02 Duncan SandsRemove the -enable-sjlj-eh option, which doesn't do...
2010-05-01 Evan ChengAdd a pseudo instruction REG_SEQUENCE that takes a...
2010-05-01 Dan GohmanGet rid of the EdgeMapping map. Instead, just check...
2010-04-29 Evan ChengFrame index can be negative.
2010-04-26 Chris Lattneron darwin empty functions need to codegen into somethin...
2010-04-26 Dale JohannesenAdd PPC AsmPrinter handling for target-specific form of
2010-04-26 Evan Cheng- Move TargetLowering::EmitTargetCodeForFrameDebugValue...
2010-04-25 Dale JohannesenStop abusing EmitInstrWithCustomInserter for target...
2010-04-22 Dan GohmanMove HandlePHINodesInSuccessorBlocks functions out...
2010-04-21 Evan ChengImplement -disable-non-leaf-fp-elim which disable frame...
2010-04-21 Dan GohmanAdd more const qualifiers on TargetMachine and friends.
2010-04-20 Dale JohannesenBecause of the EMMS problem, right now we have to support
2010-04-20 Dan GohmanDocument that TargetRegisterInfo::contains does not...
2010-04-18 Anton KorobeynikovMake processor FUs unique for given itinerary. This...
2010-04-17 Dan GohmanUse const qualifiers with TargetLowering. This eliminat...
2010-04-17 Evan ChengMore work to allow dag combiner to promote 16-bit ops...
2010-04-16 Dan GohmanAdd a getSelectionDAGInfo member to TargetMachine.
2010-04-16 Dan GohmanCreate a new TargetSelectionDAGInfo class. This will...
2010-04-16 Dan GohmanEliminate an unnecessary SelectionDAG dependency in...
2010-04-16 Dan GohmanFix this code to avoid implicit assumptions about the...
2010-04-16 Evan ChengAdding support for dag combiner to promote operations...
2010-04-15 Dan GohmanAdd const qualifiers to CodeGen's use of LLVM IR constr...
2010-04-14 Dan GohmanFactor out EH landing pad code into a separate function...
2010-04-13 Chris Lattneradd llvm codegen support for -ffunction-sections and...
2010-04-08 Evan ChengAvoid using f64 to lower memcpy from constant string...
2010-04-07 Evan ChengFix typo.
2010-04-07 Anton KorobeynikovRemove late ARM codegen optimization pass committed...
2010-04-07 Anton KorobeynikovSince tblgen bug was fixed (thanks Jakob!) we don't...
2010-04-07 Anton KorobeynikovMake use of new reserved/required scheduling stuff...
2010-04-07 Anton KorobeynikovInitial support for different kinds of FU reservation.
2010-04-07 Anton KorobeynikovAdd hook to insert late LLVM=>LLVM passes just before...
2010-04-05 Chris Lattnerunthread MMI from FastISel
2010-04-05 Chris Lattnertrim some spurious references to DwarfWriter. SDIsel...
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